UMLAL, UMLAL2 (vector)

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

The UMLAL instruction extracts vector elements from the lower half of the first source register. The UMLAL2 instruction extracts vector elements from the upper half of the first source register.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q101110size1Rm100000RnRd
Uo1

UMLAL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if size == '11' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer datasize = 64; integer part = UInt(Q); integer elements = datasize DIV esize; boolean sub_op = (o1 == '1'); boolean unsigned = (U == '1');

Assembler Symbols

2

Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is encoded in Q:

Q 2
0 [absent]
1 [present]
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>

Is an arrangement specifier, encoded in size:

size <Ta>
00 8H
01 4S
10 2D
11 RESERVED
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb>

Is an arrangement specifier, encoded in size:Q:

size Q <Tb>
00 0 8B
00 1 16B
01 0 4H
01 1 8H
10 0 2S
10 1 4S
11 x RESERVED
<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = Vpart[n, part, datasize]; bits(datasize) operand2 = Vpart[m, part, datasize]; bits(2*datasize) operand3 = V[d, 2*datasize]; bits(2*datasize) result; integer element1; integer element2; bits(2*esize) product; bits(2*esize) accum; for e = 0 to elements-1 element1 = Int(Elem[operand1, e, esize], unsigned); element2 = Int(Elem[operand2, e, esize], unsigned); product = (element1*element2)<2*esize-1:0>; if sub_op then accum = Elem[operand3, e, 2*esize] - product; else accum = Elem[operand3, e, 2*esize] + product; Elem[result, e, 2*esize] = accum; V[d, 2*datasize] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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