UQXTNB

Unsigned saturating extract narrow (bottom)

Saturate the unsigned integer value in each source element to half the original source element width, and place the results in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl000010010ZnZd
UT

UQXTNB <Zd>.<T>, <Zn>.<Tb>

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant bits(3) tsize = tszh:tszl; integer esize; case tsize of when '001' esize = 16; when '010' esize = 32; when '100' esize = 64; otherwise UNDEFINED; constant integer n = UInt(Zn); constant integer d = UInt(Zd);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in tszh:tszl:

tszh tszl <T>
0 00 RESERVED
0 01 B
0 10 H
x 11 RESERVED
1 00 S
1 01 RESERVED
1 10 RESERVED
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in tszh:tszl:

tszh tszl <Tb>
0 00 RESERVED
0 01 H
0 10 S
x 11 RESERVED
1 00 D
1 01 RESERVED
1 10 RESERVED

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(VL) operand1 = Z[n, VL]; bits(VL) result; constant integer halfesize = esize DIV 2; for e = 0 to elements-1 constant integer element1 = UInt(Elem[operand1, e, esize]); constant bits(halfesize) res = UnsignedSat(element1, halfesize); Elem[result, 2*e + 0, halfesize] = res; Elem[result, 2*e + 1, halfesize] = Zeros(halfesize); Z[d, VL] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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