UZP1, UZP2 (vectors)

Concatenate even or odd elements from two vectors

Concatenate adjacent even or odd-numbered elements from the first and second source vectors and place in elements of the destination vector. This instruction is unpredicated.

Note: UZP1 is equivalent to truncating and packing each element from two source vectors into a single destination vector with elements of half the size.

The 128-bit element variant requires that the Effective SVE vector length is at least 256 bits. ID_AA64ZFR0_EL1.F64MM indicates whether the 128-bit element variant is implemented. The 128-bit element variant is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 4 classes: Even , Even (quadwords) , Odd and Odd (quadwords)

Even

313029282726252423222120191817161514131211109876543210
00000101size1Zm011010ZnZd
H

UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer part = 0;

Even (quadwords)
(FEAT_F64MM)

313029282726252423222120191817161514131211109876543210
00000101101Zm000010ZnZd
H

UZP1 <Zd>.Q, <Zn>.Q, <Zm>.Q

if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_F64MM) then UNDEFINED; constant integer esize = 128; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer part = 0;

Odd

313029282726252423222120191817161514131211109876543210
00000101size1Zm011011ZnZd
H

UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer part = 1;

Odd (quadwords)
(FEAT_F64MM)

313029282726252423222120191817161514131211109876543210
00000101101Zm000011ZnZd
H

UZP2 <Zd>.Q, <Zn>.Q, <Zm>.Q

if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_F64MM) then UNDEFINED; constant integer esize = 128; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer part = 1;

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; if VL < esize * 2 then UNDEFINED; constant integer pairs = VL DIV (esize * 2); constant bits(VL) operand1 = Z[n, VL]; constant bits(VL) operand2 = Z[m, VL]; bits(VL) result = Zeros(VL); for p = 0 to pairs - 1 Elem[result, p, esize] = Elem[operand1, 2*p+part, esize]; for p = 0 to pairs - 1 Elem[result, pairs+p, esize] = Elem[operand2, 2*p+part, esize]; Z[d, VL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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