Zero ZA double-vector groups
The instruction zeroes one, two, or four ZA double-vector groups.
The double-vector group within all of, each half of, or each quarter of the ZA array is selected by the sum of the vector select register and offset range, modulo all, half, or quarter the number of ZA array vectors.
The vector group symbol, VGx2 or VGx4, indicates that the ZA operand consists of two or four ZA double-vector groups respectively.
It has encodings from 3 classes: One ZA double-vector , Two ZA double-vectors and Four ZA double-vectors
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | Rv | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off3 |
if !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer offset = UInt(off3:'0'); constant integer ngrp = 1; constant integer nvec = 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | Rv | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off2 |
if !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer offset = UInt(off2:'0'); constant integer ngrp = 2; constant integer nvec = 2;
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | Rv | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | off2 |
if !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer v = UInt('010':Rv); constant integer offset = UInt(off2:'0'); constant integer ngrp = 4; constant integer nvec = 2;
<Wv> |
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. |
CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer vectors = VL DIV 8; constant integer vstride = vectors DIV ngrp; constant bits(32) vbase = X[v, 32]; integer vec = (UInt(vbase) + offset) MOD vstride; vec = vec - (vec MOD nvec); for r = 0 to ngrp-1 for i = 0 to nvec-1 ZAvector[vec + i, VL] = Zeros(VL); vec = vec + vstride;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.