ZIP1, ZIP2 (predicates)

Interleave elements from two half predicates

Interleave alternating elements from the lowest or highest halves of the first and second source predicates and place in elements of the destination predicate. This instruction is unpredicated.

It has encodings from 2 classes: High halves and Low halves

High halves

313029282726252423222120191817161514131211109876543210
00000101size10Pm0100010Pn0Pd
H

ZIP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Pn); constant integer m = UInt(Pm); constant integer d = UInt(Pd); constant integer part = 1;

Low halves

313029282726252423222120191817161514131211109876543210
00000101size10Pm0100000Pn0Pd
H

ZIP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer n = UInt(Pn); constant integer m = UInt(Pm); constant integer d = UInt(Pd); constant integer part = 0;

Assembler Symbols

<Pd>

Is the name of the destination scalable predicate register, encoded in the "Pd" field.

<T>

Is the size specifier, encoded in size:

size <T>
00 B
01 H
10 S
11 D
<Pn>

Is the name of the first source scalable predicate register, encoded in the "Pn" field.

<Pm>

Is the name of the second source scalable predicate register, encoded in the "Pm" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer pairs = VL DIV (esize * 2); constant bits(PL) operand1 = P[n, PL]; constant bits(PL) operand2 = P[m, PL]; bits(PL) result; constant integer base = part * pairs; for p = 0 to pairs-1 Elem[result, 2*p+0, esize DIV 8] = Elem[operand1, base+p, esize DIV 8]; Elem[result, 2*p+1, esize DIV 8] = Elem[operand2, base+p, esize DIV 8]; P[d, PL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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