ICC_AP0R<n>

AArch32 System register ICC_AP0R<n> bits [31:0] are architecturally mapped to AArch64 System register ICC_AP0R<n>_EL1[31:0].

This register is present only when EL1 is capable of using AArch32 and GICv3 is implemented. Otherwise, direct accesses to ICC_AP0R<n> are UNDEFINED.

Attributes

Field descriptions

IMPLEMENTATION DEFINED, bits [31:0]

Additional information

Accessing ICC_AP0R<n>

Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 0 active priorities) might result in UNPREDICTABLE behavior of the interrupt prioritization system, causing:

Interrupts that should preempt execution to not preempt execution.
Interrupts that should not preempt execution to preempt execution.

ICC_AP0R1 is implemented only in implementations that support 6 or more bits of preemption. ICC_AP0R2 and ICC_AP0R3 are implemented only in implementations that support 7 bits of preemption. Unimplemented registers are UNDEFINED.

Note

The number of bits of preemption is indicated by ICH_VTR.PREbits.

Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior:

ICC_AP0R<n>.
Secure ICC_AP1R<n>.
Non-secure ICC_AP1R<n>.

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} ; Where m = 0-3

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1100	0b1000	0b1:m[1:0]

integer m = UInt(opc2<1:0>); if m == 1 && NUM_GIC_PRIORITY_BITS < 6 then UNDEFINED; elsif (m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7 then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.FIQ == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif ICC_SRE.SRE == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then R[t] = ICV_AP0R[m]; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.FMO == '1' then R[t] = ICV_AP0R[m]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch32.TakeMonitorTrapException(); else R[t] = ICC_AP0R[m]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && ELUsingAArch32(EL3) && SCR.FIQ == '1' then UNDEFINED; elsif ICC_HSRE.SRE == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch32.TakeMonitorTrapException(); else R[t] = ICC_AP0R[m]; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else R[t] = ICC_AP0R[m];

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>} ; Where m = 0-3

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1100	0b1000	0b1:m[1:0]

integer m = UInt(opc2<1:0>); if m == 1 && NUM_GIC_PRIORITY_BITS < 6 then UNDEFINED; elsif (m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7 then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.FIQ == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif ICC_SRE.SRE == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL0 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.FMO == '1' then ICV_AP0R[m] = R[t]; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.FMO == '1' then ICV_AP0R[m] = R[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch32.TakeMonitorTrapException(); else ICC_AP0R[m] = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && ELUsingAArch32(EL3) && SCR.FIQ == '1' then UNDEFINED; elsif ICC_HSRE.SRE == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.FIQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch32.TakeMonitorTrapException(); else ICC_AP0R[m] = R[t]; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else ICC_AP0R[m] = R[t];

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IMPLEMENTATION DEFINED

ICC_AP0R<n>, Interrupt Controller Active Priorities Group 0 Registers, n = 0 - 3

Purpose