The ICC_AP1R<n> characteristics are:
Provides information about Group 1 active priorities.
This register is banked between ICC_AP1R<n> and ICC_AP1R<n>_S and ICC_AP1R<n>_NS.
AArch32 System register ICC_AP1R<n> bits [31:0] (ICC_AP1R<n>_S) are architecturally mapped to AArch64 System register ICC_AP1R<n>_EL1[31:0] (ICC_AP1R<n>_EL1_S).
AArch32 System register ICC_AP1R<n> bits [31:0] (ICC_AP1R<n>_NS) are architecturally mapped to AArch64 System register ICC_AP1R<n>_EL1[31:0] (ICC_AP1R<n>_EL1_NS).
This register is present only when EL1 is capable of using AArch32 and GICv3 is implemented. Otherwise, direct accesses to ICC_AP1R<n> are UNDEFINED.
ICC_AP1R<n> is a 32-bit register.
This register has the following instances:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMPLEMENTATION DEFINED | |||||||||||||||||||||||||||||||
IMPLEMENTATION DEFINED.
The reset behavior of this field is:
The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active.
Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 1 active priorities) might result in UNPREDICTABLE behavior of the interrupt prioritization system, causing:
ICC_AP1R1 is implemented only in implementations that support 6 or more bits of preemption. ICC_AP1R2 and ICC_AP1R3 are implemented only in implementations that support 7 bits of preemption. Unimplemented registers are UNDEFINED.
The number of bits of preemption is indicated by ICH_VTR.PREbits.
Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior:
Accesses to this register use the following encodings in the System register encoding space:
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b1001 | 0b0:m[1:0] |
integer m = UInt(opc2<1:0>); if m == 1 && NUM_GIC_PRIORITY_BITS < 6 then UNDEFINED; elsif (m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7 then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.IRQ == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif ICC_SRE.SRE == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL1 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then R[t] = ICV_AP1R[m]; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.IMO == '1' then R[t] = ICV_AP1R[m]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.IRQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch32.TakeMonitorTrapException(); elsif HaveEL(EL3) then R[t] = ICC_AP1R_NS[m]; else R[t] = ICC_AP1R[m]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && ELUsingAArch32(EL3) && SCR.IRQ == '1' then UNDEFINED; elsif ICC_HSRE.SRE == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.IRQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch32.TakeMonitorTrapException(); elsif HaveEL(EL3) then R[t] = ICC_AP1R_NS[m]; else R[t] = ICC_AP1R[m]; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else if SCR.NS == '0' then R[t] = ICC_AP1R_S[m]; else R[t] = ICC_AP1R_NS[m];
| coproc | opc1 | CRn | CRm | opc2 |
|---|---|---|---|---|
| 0b1111 | 0b000 | 0b1100 | 0b1001 | 0b0:m[1:0] |
integer m = UInt(opc2<1:0>); if m == 1 && NUM_GIC_PRIORITY_BITS < 6 then UNDEFINED; elsif (m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7 then UNDEFINED; elsif PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.IRQ == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T12 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T12 == '1' then AArch32.TakeHypTrapException(0x03); elsif ICC_SRE.SRE == '0' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && ICH_HCR_EL2.TALL1 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && ICH_HCR.TALL1 == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.IMO == '1' then ICV_AP1R[m] = R[t]; elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.IMO == '1' then ICV_AP1R[m] = R[t]; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR.IRQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch32.TakeMonitorTrapException(); elsif HaveEL(EL3) then ICC_AP1R_NS[m] = R[t]; else ICC_AP1R[m] = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then UNDEFINED; elsif HaveEL(EL3) && EL3SDDUndefPriority() && ELUsingAArch32(EL3) && SCR.IRQ == '1' then UNDEFINED; elsif ICC_HSRE.SRE == '0' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && SCR_EL3.IRQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); elsif HaveEL(EL3) && ELUsingAArch32(EL3) && SCR.IRQ == '1' then if EL3SDDUndef() then UNDEFINED; else AArch32.TakeMonitorTrapException(); elsif HaveEL(EL3) then ICC_AP1R_NS[m] = R[t]; else ICC_AP1R[m] = R[t]; elsif PSTATE.EL == EL3 then if ICC_MSRE.SRE == '0' then UNDEFINED; else if SCR.NS == '0' then ICC_AP1R_S[m] = R[t]; else ICC_AP1R_NS[m] = R[t];
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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