PMEVCNTR<n>, Performance Monitors Event Count Registers, n = 0 - 30

Accessing PMEVCNTR<n>

PMEVCNTR<n> can also be accessed by using PMXEVCNTR with PMSELR.SEL set to n.

If FEAT_FGT is implemented and <n> is greater than or equal to the number of accessible event counters, then the behavior of permitted reads and writes of PMEVCNTR<n> is as follows:

• If <n> is an unimplemented event counter, the access is UNDEFINED.
• Otherwise, the access is trapped to EL2.

If FEAT_FGT is not implemented and <n> is greater than or equal to the number of accessible event counters, then reads and writes of PMEVCNTR<n> are CONSTRAINED UNPREDICTABLE, and the following behaviors are permitted:

• Accesses to the register are UNDEFINED.
• Accesses to the register behave as RAZ/WI.
• Accesses to the register execute as a NOP.
• Accesses to the register behave as if <n> is an UNKNOWN value less-than-or-equal-to the index of the highest accessible event counter.
• If EL2 is implemented and enabled in the current Security state, and <n> is less than the number of implemented event counters, accesses from EL1 or permitted accesses from EL0 are trapped to EL2.

Permitted reads and writes of PMEVCNTR<n> are RAZ/WI if all of the following are true:

• FEAT_PMUv3p9 is implemented.
• PSTATE.EL == EL0.
• EL1 is using AArch64.
• PMUSERENR_EL0.UEN == 1.
• PMUACR_EL1.P<n> == 0.

Permitted writes of PMEVCNTR<n> are ignored if all of the following are true:

• FEAT_PMUv3p9 is implemented.
• PSTATE.EL == EL0.
• EL1 is using AArch64.
• PMUSERENR_EL0.{UEN,ER} == {1,1}.

Accesses to this register use the following encodings in the System register encoding space:

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1110	0b10:m[4:3]	m[2:0]

integer m = UInt(CRm<1:0>:opc2<2:0>); if m >= NUM_PMU_COUNTERS then if IsFeatureImplemented(FEAT_FGT) then UNDEFINED; else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && ((IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.<UEN,ER,EN> == '000') || (!IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.<ER,EN> == '00')) then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && PMUSERENR.<ER,EN> == '00' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMEVCNTRn_EL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif ELUsingAArch32(EL1) then AArch32.TakeHypTrapException(0x03); else AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else if IsFeatureImplemented(FEAT_PMUv3p9) && !ELUsingAArch32(EL1) && PMUSERENR_EL0.UEN == '1' && PMUACR_EL1[m] == '0' then R[t] = Zeros(32); else R[t] = PMEVCNTR[m]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif ELUsingAArch32(EL2) then AArch32.TakeHypTrapException(0x03); else AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMEVCNTR[m]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else R[t] = PMEVCNTR[m]; elsif PSTATE.EL == EL3 then R[t] = PMEVCNTR[m];

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b1110	0b10:m[4:3]	m[2:0]

integer m = UInt(CRm<1:0>:opc2<2:0>); if m >= NUM_PMU_COUNTERS then if IsFeatureImplemented(FEAT_FGT) then UNDEFINED; else ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif !ELUsingAArch32(EL1) && (PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0.UEN == '0')) then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); else AArch64.AArch32SystemAccessTrap(EL1, 0x03); elsif ELUsingAArch32(EL1) && PMUSERENR.EN == '0' then if EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TGE == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TGE == '1' then AArch32.TakeHypTrapException(0x00); else UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL1) && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMEVCNTRn_EL0 == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif ELUsingAArch32(EL1) then AArch32.TakeHypTrapException(0x03); else AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else if IsFeatureImplemented(FEAT_PMUv3p9) && !ELUsingAArch32(EL1) && PMUSERENR_EL0.UEN == '1' && (PMUACR_EL1[m] == '0' || PMUSERENR_EL0.ER == '1') then return; else PMEVCNTR[m] = R[t]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && !ELUsingAArch32(EL2) && MDCR_EL2.TPM == '1' then AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && ELUsingAArch32(EL2) && HDCR.TPM == '1' then AArch32.TakeHypTrapException(0x03); elsif EL2Enabled() && m >= GetNumEventCountersAccessible() then if !IsFeatureImplemented(FEAT_FGT) then ConstrainUnpredictableProcedure(Unpredictable_PMUEVENTCOUNTER); elsif ELUsingAArch32(EL2) then AArch32.TakeHypTrapException(0x03); else AArch64.AArch32SystemAccessTrap(EL2, 0x03); elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMEVCNTR[m] = R[t]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && !ELUsingAArch32(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.AArch32SystemAccessTrap(EL3, 0x03); else PMEVCNTR[m] = R[t]; elsif PSTATE.EL == EL3 then PMEVCNTR[m] = R[t];