ICH_VTR

AArch64 System register ICH_VTR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_VTR[31:0].

This register is present only when GICv3 is implemented and (EL2 is implemented or EL3 is implemented). Otherwise, direct accesses to ICH_VTR_EL2 are UNDEFINED.

If EL2 is not implemented, all bits in this register are RES0 from EL3, except for nV4, which is RES1 from EL3.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

Field descriptions

Bits [63:32]

PRIbits, bits [31:29]

Priority bits. Indicates the number of virtual priority bits implemented, minus one.

An implementation must implement at least 32 levels of virtual priority (5 priority bits).

This field is an alias of ICV_CTLR_EL1.PRIbits.

The value of this field is an IMPLEMENTATION DEFINED choice of:

PRIbits	Meaning
0b100..0b110	The number of virtual priority bits implemented, minus one.

Access to this field is RO.

PREbits, bits [28:26]

Preemption bits. Indicates the number of virtual preemption bits implemented, minus one.

An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits).

The value of this field must be less than or equal to the value of ICH_VTR_EL2.PRIbits.

This field determines the minimum value of ICH_VMCR_EL2.VBPR0.

The value of this field is an IMPLEMENTATION DEFINED choice of:

PREbits	Meaning
0b000..0b110	The number of virtual preemption bits implemented, minus one.

Access to this field is RO.

IDbits, bits [25:23]

The number of virtual interrupt identifier bits supported:

The value of this field is an IMPLEMENTATION DEFINED choice of:

IDbits	Meaning
0b000	16 bits.
0b001	24 bits.

All other values are reserved.

This field is an alias of ICV_CTLR_EL1.IDbits.

Access to this field is RO.

SEIS, bit [22]

SEI Support. Indicates whether the virtual CPU interface supports generation of SEIs:

The value of this field is an IMPLEMENTATION DEFINED choice of:

SEIS	Meaning
0b0	The virtual CPU interface logic does not support generation of SEIs.
0b1	The virtual CPU interface logic supports generation of SEIs.

This bit is an alias of ICV_CTLR_EL1.SEIS.

Access to this field is RO.

A3V, bit [21]

Affinity 3 Valid.

The value of this field is an IMPLEMENTATION DEFINED choice of:

A3V	Meaning
0b0	The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers.
0b1	The virtual CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers.

This bit is an alias of ICV_CTLR_EL1.A3V.

Access to this field is RO.

nV4, bit [20]

Direct injection of virtual interrupts not supported.

The value of this field is an IMPLEMENTATION DEFINED choice of:

nV4	Meaning
0b0	The CPU interface logic supports direct injection of virtual interrupts.
0b1	The CPU interface logic does not support direct injection of virtual interrupts.

In GICv3, the only permitted value is 0b1.

Access to this field is RO.

TDS, bit [19]

Separate trapping of EL1 writes to ICV_DIR_EL1 supported.

The value of this field is an IMPLEMENTATION DEFINED choice of:

TDS	Meaning
0b0	Implementation does not support ICH_HCR_EL2.TDIR.
0b1	Implementation supports ICH_HCR_EL2.TDIR.

FEAT_GICv3_TDIR implements the functionality added by the value 0b1.

Access to this field is RO.

DVIM, bit [18]

Masking of directly-injected virtual interrupts.

The value of this field is an IMPLEMENTATION DEFINED choice of:

DVIM	Meaning
0b0	Masking of Directly-injected Virtual Interrupts not supported.
0b1	Masking of Directly-injected Virtual Interrupts is supported.

When a PE implements the Realm Management Extension, this field is RAO/WI.

Access to this field is RO.

Bits [17:5]

ListRegs, bits [4:0]

List Registers. Indicates the number of List registers implemented, minus one.

The value of this field is an IMPLEMENTATION DEFINED choice of:

ListRegs	Meaning
0b00000..0b01111	The number of List registers implemented, minus one.

Access to this field is RO.

Accessing ICH_VTR_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ICH_VTR_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b1100	0b1011	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2.SRE == '0' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ICH_VTR_EL2; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3.SRE == '0' then AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = ICH_VTR_EL2;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
PRIbits			PREbits			IDbits			SEIS	A3V	nV4	TDS	DVIM	RES0													ListRegs

ICH_VTR_EL2, Interrupt Controller VGIC Type Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:32]

PRIbits, bits [31:29]

PREbits, bits [28:26]

IDbits, bits [25:23]

SEIS, bit [22]

A3V, bit [21]

nV4, bit [20]

TDS, bit [19]

DVIM, bit [18]

Bits [17:5]

ListRegs, bits [4:0]

Accessing ICH_VTR_EL2

MRS <Xt>, ICH_VTR_EL2