The ID_AA64ISAR3_EL1 characteristics are:
Provides information about the features and instructions implemented in AArch64 state.
For general information about the interpretation of the ID registers, see 'Principles of the ID scheme for fields in ID registers'.
Prior to the introduction of the features described by this register, this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
ID_AA64ISAR3_EL1 is a 64-bit register.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | PACM | TLBIW | FAMINMAX | CPA | |||||||||||||||||||||||||||
Reserved, RES0.
Indicates the implementation of PSTATE.PACM.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| PACM | Meaning |
|---|---|
| 0b0000 |
PSTATE.PACM is not implemented. |
| 0b0001 |
Trivial implementation of PSTATE.PACM. |
| 0b0010 |
Full implementation of PSTATE.PACM. |
All other values are reserved.
FEAT_PAuth_LR implements the functionality identified by the values 0b0001 and 0b0010.
If FEAT_PAuth_LR is implemented, the value 0b0000 is not permitted.
If ID_AA64ISAR1_EL1.API is 0b0000, the value 0b0001 is not permitted.
If one of FEAT_PACQARMA3 or FEAT_PACQARMA5 are implemented, the value 0b0001 is not permitted.
Access to this field is RO.
Support for TLBI VMALL for Dirty state.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| TLBIW | Meaning |
|---|---|
| 0b0000 |
TLBI VMALL for Dirty state is not supported. |
| 0b0001 |
TLBI VMALL for Dirty state is supported. |
All other values are reserved.
FEAT_TLBIW implements the functionality identified by the value 0b0001.
Access to this field is RO.
Indicates support for the following Advanced SIMD, SVE2, and SME2 instructions that compute maximum and minimum absolute value:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| FAMINMAX | Meaning |
|---|---|
| 0b0000 |
The specified instructions are not implemented. |
| 0b0001 |
The specified instructions are implemented. |
All other values are reserved.
FEAT_FAMINMAX implements the functionality identified by the value 0b0001.
Access to this field is RO.
Indicates support for Checked Pointer Arithmetic instructions.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CPA | Meaning |
|---|---|
| 0b0000 |
Checked Pointer Arithmetic instructions are not implemented. |
| 0b0001 |
Checked Pointer Arithmetic instructions are implemented. |
| 0b0010 |
Checked Pointer Arithmetic instructions are implemented, and Checked Pointer Arithmetic can be enabled. |
All other values are reserved.
FEAT_CPA implements the functionality identified by the value 0b0001.
FEAT_CPA2 implements the functionality identified by the value 0b0010.
From Armv9.5, the value 0b0000 is not permitted.
Access to this field is RO.
Accesses to this register use the following encodings in the System register encoding space:
| op0 | op1 | CRn | CRm | op2 |
|---|---|---|---|---|
| 0b11 | 0b000 | 0b0000 | 0b0110 | 0b011 |
if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && (IsFeatureImplemented(FEAT_FGT) || !IsZero(ID_AA64ISAR3_EL1) || boolean IMPLEMENTATION_DEFINED "ID_AA64ISAR3_EL1 trapped by HCR_EL2.TID3") && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_AA64ISAR3_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_AA64ISAR3_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_AA64ISAR3_EL1;
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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