PMCCFILTR

AArch64 System register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCCFILTR[31:0].

AArch64 System register PMCCFILTR_EL0 bits [63:32] are architecturally mapped to External register PMU.PMCCFILTR_EL0[63:32] when FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented, or FEAT_PMUv3_EXT64 is implemented or FEAT_PMUv3_SME is implemented.

AArch64 System register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to External register PMU.PMCCFILTR_EL0[31:0].

This register is present only when FEAT_PMUv3 is implemented. Otherwise, direct accesses to PMCCFILTR_EL0 are UNDEFINED.

Attributes

Field descriptions

Bits [63:58]

VS, bits [57:56]
When FEAT_PMUv3_SME is implemented:

VS	Meaning
0b00	This mechanism has no effect on the filtering of cycles.
0b01	The PE does not count cycles in Streaming SVE mode.
0b10	The PE does not count cycles in Non-streaming SVE mode.

Otherwise:

Bits [55:32]

P, bit [31]

EL1 filtering. Controls counting cycles in EL1.

P	Meaning
0b0	This mechanism has no effect on filtering of cycles.
0b1	The PE does not count cycles in EL1.

If Secure and Non-secure states are implemented, then counting cycles in Non-secure EL1 is further controlled by PMCCFILTR_EL0.NSK.

If FEAT_RME is implemented, then counting cycles in Realm EL1 is further controlled by PMCCFILTR_EL0.RLK.

If EL3 is implemented, then counting cycles in EL3 is further controlled by PMCCFILTR_EL0.M.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

U, bit [30]

NSK, bit [29]
When EL3 is implemented:

Non-secure EL1 filtering. Controls counting cycles in Non-secure EL1. If PMCCFILTR_EL0.NSK is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in Non-secure EL1. Otherwise, this mechanism has no effect on filtering of cycles in Non-secure EL1.

NSK	Meaning
0b0	When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Non-secure EL1.
0b1	When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Non-secure EL1. When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

NSK

Meaning

0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Non-secure EL1.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Non-secure EL1.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

NSU, bit [28]
When EL3 is implemented:

Non-secure EL0 filtering. Controls counting cycles in Non-secure EL0. If PMCCFILTR_EL0.NSU is not equal to PMCCFILTR_EL0.U, then the PE does not count cycles in Non-secure EL0. Otherwise, this mechanism has no effect on filtering of cycles in Non-secure EL0.

NSU	Meaning
0b0	When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Non-secure EL0.
0b1	When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Non-secure EL0. When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

NSU

Meaning

0b0

When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Non-secure EL0.

0b1

When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Non-secure EL0.

When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

NSH, bit [27]
When EL2 is implemented:

NSH	Meaning
0b0	The PE does not count cycles in EL2.
0b1	This mechanism has no effect on filtering of cycles.

Otherwise:

M, bit [26]
When EL3 is implemented:

EL3 filtering. Controls counting cycles in EL3. If PMCCFILTR_EL0.M is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in EL3. Otherwise, this mechanism has no effect on filtering of cycles in EL3.

M	Meaning
0b0	When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.P == 1, the PE does not count cycles in EL3.
0b1	When PMCCFILTR_EL0.P == 0, the PE does not count cycles in EL3. When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

Meaning

0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in EL3.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in EL3.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [25]

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

Secure EL2 filtering. Controls counting cycles in Secure EL2. If PMCCFILTR_EL0.SH is equal to PMCCFILTR_EL0.NSH, then the PE does not count cycles in Secure EL2. Otherwise, this mechanism has no effect on filtering of cycles in Secure EL2.

SH	Meaning
0b0	When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Secure EL2. When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.
0b1	When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Secure EL2.

Meaning

0b0

When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Secure EL2.

When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.

0b1

When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Secure EL2.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When Secure EL2 is not implemented, access to this field is RES0 .

Otherwise:

T, bit [23]
When FEAT_TME is implemented:

T	Meaning
0b0	This bit has no effect on the filtering of cycles.
0b1	Do not count Attributable cycles in Non-transactional state.

Otherwise:

RLK, bit [22]
When FEAT_RME is implemented:

Realm EL1 filtering. Controls counting cycles in Realm EL1. If PMCCFILTR_EL0.RLK is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in Realm EL1. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL1.

RLK	Meaning
0b0	When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Realm EL1.
0b1	When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Realm EL1. When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

RLK

Meaning

0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Realm EL1.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Realm EL1.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RLU, bit [21]
When FEAT_RME is implemented:

Realm EL0 filtering. Controls counting cycles in Realm EL0. If PMCCFILTR_EL0.RLU is not equal to PMCCFILTR_EL0.U, then the PE does not count cycles in Realm EL0. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL0.

RLU	Meaning
0b0	When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Realm EL0.
0b1	When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Realm EL0. When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

RLU

Meaning

0b0

When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Realm EL0.

0b1

When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Realm EL0.

When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RLH, bit [20]
When FEAT_RME is implemented:

Realm EL2 filtering. Controls counting cycles in Realm EL2. If PMCCFILTR_EL0.RLH is equal to PMCCFILTR_EL0.NSH, then the PE does not count cycles in Realm EL2. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL2.

RLH	Meaning
0b0	When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Realm EL2. When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.
0b1	When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Realm EL2.

RLH

Meaning

0b0

When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Realm EL2.

When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.

0b1

When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Realm EL2.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [19:0]

Accessing PMCCFILTR_EL0

PMCCFILTR_EL0 can also be accessed by using PMXEVTYPER_EL0 with PMSELR_EL0.SEL set to 0b11111.

Permitted reads and writes of PMCCFILTR_EL0 are RAZ/WI if all of the following are true:

FEAT_PMUv3p9 is implemented.
PSTATE.EL == EL0.
PMUSERENR_EL0.UEN == 1.
PMUACR_EL1.C == 0.

Permitted writes of PMCCFILTR_EL0 are ignored if all of the following are true:

FEAT_PMUv3p9 is implemented.
PSTATE.EL == EL0.
PMUSERENR_EL0.{UEN,CR} == {1,1}.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMCCFILTR_EL0

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b1111	0b111

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0.UEN == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMCCFILTR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && PMUACR_EL1.C == '0' then X[t, 64] = Zeros(64); else X[t, 64] = PMCCFILTR_EL0; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMCCFILTR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMCCFILTR_EL0; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMCCFILTR_EL0; elsif PSTATE.EL == EL3 then X[t, 64] = PMCCFILTR_EL0;

MSR PMCCFILTR_EL0, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b1110	0b1111	0b111

if PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif PMUSERENR_EL0.EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0.UEN == '0') then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMCCFILTR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif IsFeatureImplemented(FEAT_PMUv3p9) && PMUSERENR_EL0.UEN == '1' && (PMUACR_EL1.C == '0' || PMUSERENR_EL0.CR == '1') then return; else PMCCFILTR_EL0 = X[t, 64]; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMCCFILTR_EL0 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMCCFILTR_EL0 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3.TPM == '1' then UNDEFINED; elsif HaveEL(EL3) && MDCR_EL3.TPM == '1' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMCCFILTR_EL0 = X[t, 64]; elsif PSTATE.EL == EL3 then PMCCFILTR_EL0 = X[t, 64];

PMCCFILTR_EL0, Performance Monitors Cycle Count Filter Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:58]

VS, bits [57:56]
When FEAT_PMUv3_SME is implemented:

Otherwise:

Bits [55:32]

P, bit [31]

U, bit [30]

NSK, bit [29]
When EL3 is implemented:

Otherwise:

NSU, bit [28]
When EL3 is implemented:

Otherwise:

NSH, bit [27]
When EL2 is implemented:

Otherwise:

M, bit [26]
When EL3 is implemented:

Otherwise:

Bit [25]

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

Otherwise:

T, bit [23]
When FEAT_TME is implemented:

Otherwise:

RLK, bit [22]
When FEAT_RME is implemented:

Otherwise:

RLU, bit [21]
When FEAT_RME is implemented:

Otherwise:

RLH, bit [20]
When FEAT_RME is implemented:

Otherwise:

Bits [19:0]

Accessing PMCCFILTR_EL0

MRS <Xt>, PMCCFILTR_EL0

MSR PMCCFILTR_EL0, <Xt>

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0						VS		RES0
P	U	NSK	NSU	NSH	M	RES0	SH	T	RLK	RLU	RLH	RES0

U	Meaning
0b0	This mechanism has no effect on filtering of cycles.
0b1	The PE does not count cycles in EL0.

PMCCFILTR_EL0, Performance Monitors Cycle Count Filter Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:58]

VS, bits [57:56]When FEAT_PMUv3_SME is implemented:

Otherwise:

Bits [55:32]

P, bit [31]

U, bit [30]

NSK, bit [29]When EL3 is implemented:

Otherwise:

NSU, bit [28]When EL3 is implemented:

Otherwise:

NSH, bit [27]When EL2 is implemented:

Otherwise:

M, bit [26]When EL3 is implemented:

Otherwise:

Bit [25]

SH, bit [24]When EL3 is implemented and FEAT_SEL2 is implemented:

Otherwise:

T, bit [23]When FEAT_TME is implemented:

Otherwise:

RLK, bit [22]When FEAT_RME is implemented:

Otherwise:

RLU, bit [21]When FEAT_RME is implemented:

Otherwise:

RLH, bit [20]When FEAT_RME is implemented:

Otherwise:

Bits [19:0]

Accessing PMCCFILTR_EL0

MRS <Xt>, PMCCFILTR_EL0

MSR PMCCFILTR_EL0, <Xt>

VS, bits [57:56]
When FEAT_PMUv3_SME is implemented:

NSK, bit [29]
When EL3 is implemented:

NSU, bit [28]
When EL3 is implemented:

NSH, bit [27]
When EL2 is implemented:

M, bit [26]
When EL3 is implemented:

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

T, bit [23]
When FEAT_TME is implemented:

RLK, bit [22]
When FEAT_RME is implemented:

RLU, bit [21]
When FEAT_RME is implemented:

RLH, bit [20]
When FEAT_RME is implemented: