PMCCFILTR

External register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMCCFILTR_EL0[31:0] when FEAT_PMUv3_EXT32 is implemented.

External register PMCCFILTR_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMCCFILTR_EL0[63:0] when FEAT_PMUv3_EXT64 is implemented, or FEAT_PMUv3_TH is implemented or FEAT_PMUv3p8 is implemented.

External register PMCCFILTR_EL0 bits [31:0] are architecturally mapped to AArch32 System register PMCCFILTR[31:0].

This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCCFILTR_EL0 are RES0.

Attributes

Field descriptions

Bits [63:58]

VS, bits [57:56]
When FEAT_PMUv3_SME is implemented:

SVE mode filtering. Controls counting cycles in Streaming and Non-streaming SVE modes.

VS	Meaning
0b00	This mechanism has no effect on the filtering of cycles.
0b01	The PE does not count cycles in Streaming SVE mode.
0b10	The PE does not count cycles in Non-streaming SVE mode.

All other values are reserved.

The reset behavior of this field is:

On a Warm reset:
- When AArch32 is supported, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [55:32]

P, bit [31]

EL1 filtering. Controls counting cycles in EL1.

P	Meaning
0b0	This mechanism has no effect on filtering of cycles.
0b1	The PE does not count cycles in EL1.

If Secure and Non-secure states are implemented, then counting cycles in Non-secure EL1 is further controlled by PMCCFILTR_EL0.NSK.

If FEAT_RME is implemented, then counting cycles in Realm EL1 is further controlled by PMCCFILTR_EL0.RLK.

If EL3 is implemented, then counting cycles in EL3 is further controlled by PMCCFILTR_EL0.M.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

U, bit [30]

EL0 filtering. Controls counting cycles in EL0.

U	Meaning
0b0	This mechanism has no effect on filtering of cycles.
0b1	The PE does not count cycles in EL0.

If Secure and Non-secure states are implemented, then counting cycles in Non-secure EL0 is further controlled by PMCCFILTR_EL0.NSU.

If FEAT_RME is implemented, then counting cycles in Realm EL0 is further controlled by PMCCFILTR_EL0.RLU.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

NSK, bit [29]
When EL3 is implemented:

Non-secure EL1 filtering. Controls counting cycles in Non-secure EL1. If PMCCFILTR_EL0.NSK is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in Non-secure EL1. Otherwise, this mechanism has no effect on filtering of cycles in Non-secure EL1.

NSK	Meaning
0b0	When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Non-secure EL1.
0b1	When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Non-secure EL1. When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

NSK

Meaning

0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Non-secure EL1.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Non-secure EL1.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset:
- When the implementation only supports execution in AArch32 state, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

NSU, bit [28]
When EL3 is implemented:

Non-secure EL0 filtering. Controls counting cycles in Non-secure EL0. If PMCCFILTR_EL0.NSU is not equal to PMCCFILTR_EL0.U, then the PE does not count cycles in Non-secure EL0. Otherwise, this mechanism has no effect on filtering of cycles in Non-secure EL0.

NSU	Meaning
0b0	When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Non-secure EL0.
0b1	When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Non-secure EL0. When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

NSU

Meaning

0b0

When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Non-secure EL0.

0b1

When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Non-secure EL0.

When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset:
- When the implementation only supports execution in AArch32 state, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

NSH, bit [27]
When EL2 is implemented:

EL2 filtering. Controls counting cycles in EL2.

NSH	Meaning
0b0	The PE does not count cycles in EL2.
0b1	This mechanism has no effect on filtering of cycles.

If EL3 is implemented and FEAT_SEL2 is implemented, then counting cycles in Secure EL2 is further controlled by PMCCFILTR_EL0.SH.

If FEAT_RME is implemented, then counting cycles in Realm EL2 is further controlled by PMCCFILTR_EL0.RLH.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

M, bit [26]
When EL3 is implemented and AArch64 is supported:

EL3 filtering. Controls counting cycles in EL3. If PMCCFILTR_EL0.M is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in EL3. Otherwise, this mechanism has no effect on filtering of cycles in EL3.

M	Meaning
0b0	When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.P == 1, the PE does not count cycles in EL3.
0b1	When PMCCFILTR_EL0.P == 0, the PE does not count cycles in EL3. When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

Meaning

0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in EL3.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in EL3.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [25]

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

Secure EL2 filtering. Controls counting cycles in Secure EL2. If PMCCFILTR_EL0.SH is equal to PMCCFILTR_EL0.NSH, then the PE does not count cycles in Secure EL2. Otherwise, this mechanism has no effect on filtering of cycles in Secure EL2.

SH	Meaning
0b0	When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Secure EL2. When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.
0b1	When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Secure EL2.

Meaning

0b0

When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Secure EL2.

When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.

0b1

When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Secure EL2.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When Secure EL2 is not implemented, access to this field is RES0 .

Otherwise:

T, bit [23]
When FEAT_TME is implemented:

Non-Transactional state filtering bit. Controls counting of cycles in Non-transactional state.

T	Meaning
0b0	This bit has no effect on the filtering of cycles.
0b1	Do not count Attributable cycles in Non-transactional state.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RLK, bit [22]
When FEAT_RME is implemented:

Realm EL1 filtering. Controls counting cycles in Realm EL1. If PMCCFILTR_EL0.RLK is not equal to PMCCFILTR_EL0.P, then the PE does not count cycles in Realm EL1. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL1.

RLK	Meaning
0b0	When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Realm EL1.
0b1	When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Realm EL1. When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

RLK

Meaning

0b0

When PMCCFILTR_EL0.P == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.P == 1, the PE does not count cycles in Realm EL1.

0b1

When PMCCFILTR_EL0.P == 0, the PE does not count cycles in Realm EL1.

When PMCCFILTR_EL0.P == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RLU, bit [21]
When FEAT_RME is implemented:

Realm EL0 filtering. Controls counting cycles in Realm EL0. If PMCCFILTR_EL0.RLU is not equal to PMCCFILTR_EL0.U, then the PE does not count cycles in Realm EL0. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL0.

RLU	Meaning
0b0	When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Realm EL0.
0b1	When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Realm EL0. When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

RLU

Meaning

0b0

When PMCCFILTR_EL0.U == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.U == 1, the PE does not count cycles in Realm EL0.

0b1

When PMCCFILTR_EL0.U == 0, the PE does not count cycles in Realm EL0.

When PMCCFILTR_EL0.U == 1, this mechanism has no effect on filtering of cycles.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

RLH, bit [20]
When FEAT_RME is implemented:

Realm EL2 filtering. Controls counting cycles in Realm EL2. If PMCCFILTR_EL0.RLH is equal to PMCCFILTR_EL0.NSH, then the PE does not count cycles in Realm EL2. Otherwise, this mechanism has no effect on filtering of cycles in Realm EL2.

RLH	Meaning
0b0	When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Realm EL2. When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.
0b1	When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles. When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Realm EL2.

RLH

Meaning

0b0

When PMCCFILTR_EL0.NSH == 0, the PE does not count cycles in Realm EL2.

When PMCCFILTR_EL0.NSH == 1, this mechanism has no effect on filtering of cycles.

0b1

When PMCCFILTR_EL0.NSH == 0, this mechanism has no effect on filtering of cycles.

When PMCCFILTR_EL0.NSH == 1, the PE does not count cycles in Realm EL2.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [19:0]

Accessing PMCCFILTR_EL0

If FEAT_PMUv3_EXT32 is implemented, and any of the following apply, then bits [63:32] of this register are accessible at offset 0xA7C:

FEAT_PMUv3_TH is implemented.
FEAT_PMUv3p8 is implemented.
FEAT_PMUv3_SME is implemented.

Otherwise accesses at this offset are IMPLEMENTATION DEFINED.

Note

SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.

Accesses to this register use the following encodings:

When FEAT_PMUv3_EXT32 is implemented

[31:0] Accessible at offset 0x47C from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
When SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

When FEAT_PMUv3_EXT64 is implemented

Accessible at offset 0x4F8 from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
Otherwise, accesses to this register are RW.

When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented or FEAT_PMUv3_SME is implemented)

[63:32] Accessible at offset 0xA7C from PMU

When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
When SoftwareLockStatus(), accesses to this register are RO.
Otherwise, accesses to this register are RW.

PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:58]

VS, bits [57:56]
When FEAT_PMUv3_SME is implemented:

Otherwise:

Bits [55:32]

P, bit [31]

U, bit [30]

NSK, bit [29]
When EL3 is implemented:

Otherwise:

NSU, bit [28]
When EL3 is implemented:

Otherwise:

NSH, bit [27]
When EL2 is implemented:

Otherwise:

M, bit [26]
When EL3 is implemented and AArch64 is supported:

Otherwise:

Bit [25]

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

Otherwise:

T, bit [23]
When FEAT_TME is implemented:

Otherwise:

RLK, bit [22]
When FEAT_RME is implemented:

Otherwise:

RLU, bit [21]
When FEAT_RME is implemented:

Otherwise:

RLH, bit [20]
When FEAT_RME is implemented:

Otherwise:

Bits [19:0]

Accessing PMCCFILTR_EL0

When FEAT_PMUv3_EXT32 is implemented

When FEAT_PMUv3_EXT64 is implemented

When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented or FEAT_PMUv3_SME is implemented)

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0						VS		RES0
P	U	NSK	NSU	NSH	M	RES0	SH	T	RLK	RLU	RLH	RES0

PMCCFILTR_EL0, Performance Monitors Cycle Counter Filter Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:58]

VS, bits [57:56]When FEAT_PMUv3_SME is implemented:

Otherwise:

Bits [55:32]

P, bit [31]

U, bit [30]

NSK, bit [29]When EL3 is implemented:

Otherwise:

NSU, bit [28]When EL3 is implemented:

Otherwise:

NSH, bit [27]When EL2 is implemented:

Otherwise:

M, bit [26]When EL3 is implemented and AArch64 is supported:

Otherwise:

Bit [25]

SH, bit [24]When EL3 is implemented and FEAT_SEL2 is implemented:

Otherwise:

T, bit [23]When FEAT_TME is implemented:

Otherwise:

RLK, bit [22]When FEAT_RME is implemented:

Otherwise:

RLU, bit [21]When FEAT_RME is implemented:

Otherwise:

RLH, bit [20]When FEAT_RME is implemented:

Otherwise:

Bits [19:0]

Accessing PMCCFILTR_EL0

When FEAT_PMUv3_EXT32 is implemented

When FEAT_PMUv3_EXT64 is implemented

When FEAT_PMUv3_EXT32 is implemented and (FEAT_PMUv3_TH is implemented, or FEAT_PMUv3p8 is implemented or FEAT_PMUv3_SME is implemented)

VS, bits [57:56]
When FEAT_PMUv3_SME is implemented:

NSK, bit [29]
When EL3 is implemented:

NSU, bit [28]
When EL3 is implemented:

NSH, bit [27]
When EL2 is implemented:

M, bit [26]
When EL3 is implemented and AArch64 is supported:

SH, bit [24]
When EL3 is implemented and FEAT_SEL2 is implemented:

T, bit [23]
When FEAT_TME is implemented:

RLK, bit [22]
When FEAT_RME is implemented:

RLU, bit [21]
When FEAT_RME is implemented:

RLH, bit [20]
When FEAT_RME is implemented: