AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
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Proprietary Notice

PMSEVFR_EL1, Sampling Event Filter Register

The PMSEVFR_EL1 characteristics are:

Purpose

Controls sample filtering by events. The overall filter is the logical AND of these filters. For example, if PMSEVFR_EL1.E[3] and PMSEVFR_EL1.E[5] are both set to 1, only samples that have both event 3 (Level 1 unified or data cache refill) and event 5 (TLB walk) set to 1 are recorded.

Configuration

This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSEVFR_EL1 are UNDEFINED.

Attributes

PMSEVFR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
E[63]E[62]E[61]E[60]E[59]E[58]E[57]E[56]E[55]E[54]E[53]E[52]E[51]E[50]E[49]E[48]RAZ/WI
E[31]E[30]E[29]E[28]E[27]E[26]E[25]E[24]E[23]E[22]E[21]E[20]E[19]E[18]E[17]E[16]E[15]E[14]E[13]E[12]E[11]E[10]E[9]E[8]E[7]E[6]E[5]E[4]E[3]E[2]E[1]RAZ/WI

E[63], bit [63]
When event 63 is implemented and filtering on event 63 is supported:

Filter on IMPLEMENTATION DEFINED event 63.

E[63]Meaning
0b0

Event 63 is ignored.

0b1

Do not record samples that have event 63 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[62], bit [62]
When event 62 is implemented and filtering on event 62 is supported:

Filter on IMPLEMENTATION DEFINED event 62.

E[62]Meaning
0b0

Event 62 is ignored.

0b1

Do not record samples that have event 62 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[61], bit [61]
When event 61 is implemented and filtering on event 61 is supported:

Filter on IMPLEMENTATION DEFINED event 61.

E[61]Meaning
0b0

Event 61 is ignored.

0b1

Do not record samples that have event 61 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[60], bit [60]
When event 60 is implemented and filtering on event 60 is supported:

Filter on IMPLEMENTATION DEFINED event 60.

E[60]Meaning
0b0

Event 60 is ignored.

0b1

Do not record samples that have event 60 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[59], bit [59]
When event 59 is implemented and filtering on event 59 is supported:

Filter on IMPLEMENTATION DEFINED event 59.

E[59]Meaning
0b0

Event 59 is ignored.

0b1

Do not record samples that have event 59 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[58], bit [58]
When event 58 is implemented and filtering on event 58 is supported:

Filter on IMPLEMENTATION DEFINED event 58.

E[58]Meaning
0b0

Event 58 is ignored.

0b1

Do not record samples that have event 58 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[57], bit [57]
When event 57 is implemented and filtering on event 57 is supported:

Filter on IMPLEMENTATION DEFINED event 57.

E[57]Meaning
0b0

Event 57 is ignored.

0b1

Do not record samples that have event 57 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[56], bit [56]
When event 56 is implemented and filtering on event 56 is supported:

Filter on IMPLEMENTATION DEFINED event 56.

E[56]Meaning
0b0

Event 56 is ignored.

0b1

Do not record samples that have event 56 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[55], bit [55]
When event 55 is implemented and filtering on event 55 is supported:

Filter on IMPLEMENTATION DEFINED event 55.

E[55]Meaning
0b0

Event 55 is ignored.

0b1

Do not record samples that have event 55 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[54], bit [54]
When event 54 is implemented and filtering on event 54 is supported:

Filter on IMPLEMENTATION DEFINED event 54.

E[54]Meaning
0b0

Event 54 is ignored.

0b1

Do not record samples that have event 54 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[53], bit [53]
When event 53 is implemented and filtering on event 53 is supported:

Filter on IMPLEMENTATION DEFINED event 53.

E[53]Meaning
0b0

Event 53 is ignored.

0b1

Do not record samples that have event 53 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[52], bit [52]
When event 52 is implemented and filtering on event 52 is supported:

Filter on IMPLEMENTATION DEFINED event 52.

E[52]Meaning
0b0

Event 52 is ignored.

0b1

Do not record samples that have event 52 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[51], bit [51]
When event 51 is implemented and filtering on event 51 is supported:

Filter on IMPLEMENTATION DEFINED event 51.

E[51]Meaning
0b0

Event 51 is ignored.

0b1

Do not record samples that have event 51 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[50], bit [50]
When event 50 is implemented and filtering on event 50 is supported:

Filter on IMPLEMENTATION DEFINED event 50.

E[50]Meaning
0b0

Event 50 is ignored.

0b1

Do not record samples that have event 50 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[49], bit [49]
When event 49 is implemented and filtering on event 49 is supported:

Filter on IMPLEMENTATION DEFINED event 49.

E[49]Meaning
0b0

Event 49 is ignored.

0b1

Do not record samples that have event 49 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[48], bit [48]
When event 48 is implemented and filtering on event 48 is supported:

Filter on IMPLEMENTATION DEFINED event 48.

E[48]Meaning
0b0

Event 48 is ignored.

0b1

Do not record samples that have event 48 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

Bits [47:32]

Reserved, RAZ/WI.

E[31], bit [31]
When FEAT_SPEv1p4 is not implemented, event 31 is implemented and filtering on event 31 is supported:

Filter on IMPLEMENTATION DEFINED event 31.

E[31]Meaning
0b0

Event 31 is ignored.

0b1

Do not record samples that have event 31 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[30], bit [30]
When FEAT_SPEv1p4 is not implemented, event 30 is implemented and filtering on event 30 is supported:

Filter on IMPLEMENTATION DEFINED event 30.

E[30]Meaning
0b0

Event 30 is ignored.

0b1

Do not record samples that have event 30 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[29], bit [29]
When FEAT_SPEv1p4 is not implemented, event 29 is implemented and filtering on event 29 is supported:

Filter on IMPLEMENTATION DEFINED event 29.

E[29]Meaning
0b0

Event 29 is ignored.

0b1

Do not record samples that have event 29 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[28], bit [28]
When FEAT_SPEv1p4 is not implemented, event 28 is implemented and filtering on event 28 is supported:

Filter on IMPLEMENTATION DEFINED event 28.

E[28]Meaning
0b0

Event 28 is ignored.

0b1

Do not record samples that have event 28 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[27], bit [27]
When FEAT_SPEv1p4 is not implemented, event 27 is implemented and filtering on event 27 is supported:

Filter on IMPLEMENTATION DEFINED event 27.

E[27]Meaning
0b0

Event 27 is ignored.

0b1

Do not record samples that have event 27 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[26], bit [26]
When FEAT_SPEv1p4 is not implemented, event 26 is implemented and filtering on event 26 is supported:

Filter on IMPLEMENTATION DEFINED event 26.

E[26]Meaning
0b0

Event 26 is ignored.

0b1

Do not record samples that have event 26 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[25], bit [25]
When FEAT_SPE_SME is implemented and event 25 is implemented:

Filter on SMCU or external coprocessor operation event.

E[25]Meaning
0b0

SMCU or external coprocessor operation event is ignored.

0b1

Do not record samples that have the SMCU or external coprocessor operation event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


When FEAT_SPEv1p4 is not implemented, event 25 is implemented and filtering on event 25 is supported:

Filter on IMPLEMENTATION DEFINED event 25.

E[25]Meaning
0b0

Event 25 is ignored.

0b1

Do not record samples that have event 25 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[24], bit [24]
When FEAT_SPE_SME is implemented:

Filter on Streaming SVE mode event.

E[24]Meaning
0b0

Streaming SVE mode event is ignored.

0b1

Do not record samples that have the Streaming SVE mode event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


When FEAT_SPEv1p4 is not implemented, event 24 is implemented and filtering on event 24 is supported:

Filter on IMPLEMENTATION DEFINED event 24.

E[24]Meaning
0b0

Event 24 is ignored.

0b1

Do not record samples that have event 24 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[23], bit [23]
When FEAT_SPEv1p4 is implemented and event 23 is implemented:

Filter on Data snooped event.

E[23]Meaning
0b0

Data snooped event is ignored.

0b1

Do not record samples that have the Data snooped event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[22], bit [22]
When FEAT_SPEv1p4 is implemented and event 22 is implemented:

Filter on Recently fetched event.

E[22]Meaning
0b0

Recently fetched event is ignored.

0b1

Do not record samples that have the Recently fetched event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[21], bit [21]
When FEAT_SPEv1p4 is implemented and event 21 is implemented:

Filter on Cache data modified event.

E[21]Meaning
0b0

Cache data modified event is ignored.

0b1

Do not record samples that have the Cache data modified event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[20], bit [20]
When FEAT_SPEv1p4 is implemented and event 20 is implemented:

Filter on Level 2 data cache miss event.

E[20]Meaning
0b0

Level 2 data cache miss event is ignored.

0b1

Do not record samples that have the Level 2 data cache miss event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[19], bit [19]
When FEAT_SPEv1p4 is implemented and event 19 is implemented:

Filter on Level 2 data cache access event.

E[19]Meaning
0b0

Level 2 data cache access event is ignored.

0b1

Do not record samples that have the Level 2 data cache access event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[18], bit [18]
When FEAT_SPEv1p1 is implemented and FEAT_SVE is implemented:

Filter on Empty predicate event.

E[18]Meaning
0b0

Empty predicate event is ignored.

0b1

Do not record samples that have the Empty predicate event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[17], bit [17]
When FEAT_SPEv1p1 is implemented and FEAT_SVE is implemented:

Filter on Partial or empty predicate event.

E[17]Meaning
0b0

Partial or empty predicate event is ignored.

0b1

Do not record samples that have the Partial or empty predicate event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[16], bit [16]
When FEAT_TME is implemented:

Filter on Transactional event.

E[16]Meaning
0b0

Transactional event is ignored.

0b1

Do not record samples that have the Transactional event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[15], bit [15]
When event 15 is implemented and filtering on event 15 is supported:

Filter on IMPLEMENTATION DEFINED event 15.

E[15]Meaning
0b0

Event 15 is ignored.

0b1

Do not record samples that have event 15 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[14], bit [14]
When event 14 is implemented and filtering on event 14 is supported:

Filter on IMPLEMENTATION DEFINED event 14.

E[14]Meaning
0b0

Event 14 is ignored.

0b1

Do not record samples that have event 14 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[13], bit [13]
When event 13 is implemented and filtering on event 13 is supported:

Filter on IMPLEMENTATION DEFINED event 13.

E[13]Meaning
0b0

Event 13 is ignored.

0b1

Do not record samples that have event 13 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[12], bit [12]
When event 12 is implemented and filtering on event 12 is supported:

Filter on IMPLEMENTATION DEFINED event 12.

E[12]Meaning
0b0

Event 12 is ignored.

0b1

Do not record samples that have event 12 == 0.

An IMPLEMENTATION DEFINED event might be recorded as a multi-bit field. In this case, the corresponding bits of PMSEVFR_EL1 define an IMPLEMENTATION DEFINED filter for the event.

This field is ignored by the PE when PMSFCR_EL1.FE == 0

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[11], bit [11]
When FEAT_SPEv1p1 is implemented:

Filter on Misalignment event.

E[11]Meaning
0b0

Misalignment event is ignored.

0b1

Do not record samples that have the Misalignment event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[10], bit [10]
When (FEAT_SPEv1p4 is implemented or filtering on event 10 is optionally supported) and event 10 is implemented:

Filter on Remote access event.

E[10]Meaning
0b0

Remote access event is ignored.

0b1

Do not record samples that have the Remote access event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[9], bit [9]
When (FEAT_SPEv1p4 is implemented or filtering on event 9 is optionally supported) and event 9 is implemented:

Filter on Last Level cache miss event.

E[9]Meaning
0b0

Last Level cache miss event is ignored.

0b1

Do not record samples that have the Last Level cache miss event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[8], bit [8]
When (FEAT_SPEv1p4 is implemented or filtering on event 8 is optionally supported) and event 8 is implemented:

Filter on Last Level cache access event.

E[8]Meaning
0b0

Last Level cache access event is ignored.

0b1

Do not record samples that have the Last Level cache access event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[7], bit [7]

Filter on Mispredicted event.

E[7]Meaning
0b0

Mispredicted event is ignored.

0b1

Do not record samples that have the Mispredicted event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:

E[6], bit [6]
When FEAT_SPEv1p2 is implemented:

Filter on Not taken event.

E[6]Meaning
0b0

Not taken event is ignored.

0b1

Do not record samples that have the Not taken event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[5], bit [5]

Filter on TLB walk event.

E[5]Meaning
0b0

TLB walk event is ignored.

0b1

Do not record samples that have the TLB walk event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:

E[4], bit [4]
When FEAT_SPEv1p4 is implemented or filtering on event 4 is optionally supported:

Filter on TLB access event.

E[4]Meaning
0b0

TLB access event is ignored.

0b1

Do not record samples that have the TLB access event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[3], bit [3]

Filter on Level 1 data cache refill or miss event.

E[3]Meaning
0b0

Level 1 data cache refill or miss event is ignored.

0b1

Do not record samples that have the Level 1 data cache refill or miss event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:

E[2], bit [2]
When FEAT_SPEv1p4 is implemented or filtering on event 2 is optionally supported:

Filter on Level 1 data cache access event.

E[2]Meaning
0b0

Level 1 data cache access event is ignored.

0b1

Do not record samples that have the Level 1 data cache access event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

E[1], bit [1]
When the PE supports sampling of speculative instructions:

Filter on Architecturally retired event.

E[1]Meaning
0b0

Architecturally retired event is ignored.

0b1

Do not record samples that have the Architecturally retired event == 0.

This field is ignored by the PE when PMSFCR_EL1.FE == 0.

If the PE does not support the sampling of speculative instructions, or always discards the sample record for speculative instructions, this bit reads as an UNKNOWN value and the PE ignores its value.

The reset behavior of this field is:


Otherwise:

Reserved, UNKNOWN.

Bit [0]

Reserved, RAZ/WI.

Accessing PMSEVFR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMSEVFR_EL1

op0op1CRnCRmop2
0b110b0000b10010b10010b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMSEVFR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x830]; else X[t, 64] = PMSEVFR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSEVFR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMSEVFR_EL1;

MSR PMSEVFR_EL1, <Xt>

op0op1CRnCRmop2
0b110b0000b10010b10010b101

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMSEVFR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); elsif EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x830] = X[t, 64]; else PMSEVFR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSEVFR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMSEVFR_EL1 = X[t, 64];

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
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Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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