PMSFCR

Controls sample filtering. The filter is the logical AND of the FL, FT and FE bits. For example, if FE == 1 and FT == 1 only samples including the selected operation types and the selected events will be recorded

Configuration

This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSFCR_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:53]

SIMDm, bit [52]
When FEAT_SPE_EFT is implemented:

SIMD filter mask.

SIMDm	Meaning
0b0	PMSFCR_EL1.SIMD controls whether SIMD operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls.
0b1	PMSFCR_EL1.SIMD controls whether SIMD operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

FPm, bit [51]
When FEAT_SPE_EFT is implemented:

Floating-point filter mask.

FPm	Meaning
0b0	PMSFCR_EL1.FP controls whether floating-point operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls.
0b1	PMSFCR_EL1.FP controls whether floating-point operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

STm, bit [50]
When FEAT_SPE_EFT is implemented:

Store filter mask.

STm	Meaning
0b0	PMSFCR_EL1.ST controls whether store operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls.
0b1	PMSFCR_EL1.ST controls whether store operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

LDm, bit [49]
When FEAT_SPE_EFT is implemented:

Load filter mask.

LDm	Meaning
0b0	PMSFCR_EL1.LD controls whether load operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls.
0b1	PMSFCR_EL1.LD controls whether load operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bm, bit [48]
When FEAT_SPE_EFT is implemented:

Branch filter mask.

Bm	Meaning
0b0	PMSFCR_EL1.B controls whether branch operations are recorded as part of a Boolean-OR filter with other masked operation type filter controls.
0b1	PMSFCR_EL1.B controls whether branch operations are recorded as part of a Boolean-AND filter with other unmasked operation type filter controls.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [47:21]

SIMD, bit [20]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.SIMDm == 1:

SIMD filter value.

SIMD	Meaning
0b0	Record only operations that are not SIMD operations.
0b1	Record only operations that are SIMD operations.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, SIMD operations include Advanced SIMD, SVE, and SME SIMD operations.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When FEAT_SPE_EFT is implemented:

SIMD filter enable.

SIMD	Meaning
0b0	Do not record SIMD operations, unless enabled by another filter.
0b1	Record all SIMD operations

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, SIMD operations include Advanced SIMD, SVE, and SME SIMD operations.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

FP, bit [19]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.FPm == 1:

Floating-point filter value.

FP	Meaning
0b0	Record only operations that are not floating-point operations.
0b1	Record only operations that are floating-point operations.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, floating-point operations include scalar, Advanced SIMD, SVE, and SME floating-point operations, as defined by the FP_SPEC event.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

When FEAT_SPE_EFT is implemented:

Floating-point filter enable.

FP	Meaning
0b0	Do not record floating-point operations, unless enabled by another filter.
0b1	Record all floating-point operations

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, floating-point operations include scalar, Advanced SIMD, SVE, and SME floating-point operations, as defined by the FP_SPEC event.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

ST, bit [18]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.STm == 1:

Store filter value.

ST	Meaning
0b0	Record only operations that are not store operations.
0b1	Record only operations that are store operations.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, store operations include vector stores and all atomic operations.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Store filter enable.

ST	Meaning
0b0	Do not record store operations, unless enabled by another filter.
0b1	Record all store operations

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, store operations include vector stores and all atomic operations.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

LD, bit [17]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.LDm == 1:

Load filter value.

LD	Meaning
0b0	Record only operations that are not load operations.
0b1	Record only operations that are load operations.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, load operations include vector loads and atomic operations that return a value to the PE.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Load filter enable.

LD	Meaning
0b0	Do not record load operations, unless enabled by another filter.
0b1	Record all load operations

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, load operations include vector loads and atomic operations that return a value to the PE.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

B, bit [16]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.Bm == 1:

Branch filter value.

B	Meaning
0b0	Record only operations that are not branch operations.
0b1	Record only operations that are branch operations.

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, branch operations include exception returns.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Branch filter enable.

B	Meaning
0b0	Do not record branch operations, unless enabled by another filter.
0b1	Record all branch operations

This field is ignored by the PE when PMSFCR_EL1.FT == 0.

For filtering purposes, branch operations include exception returns.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bits [15:5]

FDS, bit [4]
When FEAT_SPE_FDS is implemented:

Filter by Data Source.

FDS	Meaning
0b0	Data Source filtering disabled.
0b1	Data Source filtering enabled. Samples of load instructions reporting a Data Source not selected by PMSDSFR_EL1 will not be recorded.

If PMSFCR_EL1.FDS == 1 and PMSDSFR_EL1 is zero, then no load operations with a Data Source will be recorded.

Load operations without a Data Source and other sampled operations are unaffected by this field.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

FnE, bit [3]
When FEAT_SPEv1p2 is implemented:

Filter by event, inverted.

FnE	Meaning
0b0	Inverted event filtering disabled.
0b1	Inverted event filtering enabled. Samples including the events selected by PMSNEVFR_EL1 will not be recorded.

If any of the following are true, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FnE == 0:

PMSFCR_EL1.FnE == 1 and PMSNEVFR_EL1 is zero.
PMSFCR_EL1.FnE == 1, PMSFCR_EL1.FE == 1, and there exists a value x such that PMSEVFR_EL1.E[x] == 1 and PMSNEVFR_EL1.E[x] == 1.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

FL, bit [2]

Filter by latency

FL	Meaning
0b0	Latency filtering disabled
0b1	Latency filtering enabled. Samples with a total latency less than PMSLATFR_EL1.MINLAT will not be recorded

If this field is set to 1 and PMSLATFR_EL1.MINLAT is set to zero, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FL is set to 0

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

FT, bit [1]

Filter by operation type. The filter is the logical OR of the ST, LD and B bits. For example, if LD and ST are both set, both load and store operations are recorded

FT	Meaning
0b0	Type filtering disabled
0b1	Type filtering enabled. Samples not one of the selected operation types will not be recorded

If this field is set to 1 and the PMSFCR_EL1.{ST, LD, B} bits are all set to zero, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FT is set to 0

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

FE, bit [0]

Filter by event.

FE	Meaning
0b0	Event filtering disabled.
0b1	Event filtering enabled. Samples not including the events selected by PMSEVFR_EL1 will not be recorded.

If any of the following are true, it is CONSTRAINED UNPREDICTABLE whether no samples are recorded or the PE behaves as if PMSFCR_EL1.FE == 0:

PMSFCR_EL1.FE == 1 and PMSEVFR_EL1 is zero.
FEAT_SPEv1p2 is implemented, PMSFCR_EL1.FnE == 1, PMSFCR_EL1.FE == 1, and there exists a value x such that PMSEVFR_EL1.E[x] == 1 and PMSNEVFR_EL1.E[x] == 1.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing PMSFCR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMSFCR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1001	0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGRTR_EL2.PMSFCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSFCR_EL1; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = PMSFCR_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = PMSFCR_EL1;

MSR PMSFCR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1001	0b100

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HDFGWTR_EL2.PMSFCR_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2.TPMS == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSFCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then UNDEFINED; elsif HaveEL(EL3) && (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) && MDCR_EL3.NSPBE != SCR_EL3.NSE)) then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else PMSFCR_EL1 = X[t, 64]; elsif PSTATE.EL == EL3 then PMSFCR_EL1 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0											SIMDm	FPm	STm	LDm	Bm	RES0
RES0											SIMD	FP	ST	LD	B	RES0											FDS	FnE	FL	FT	FE

PMSFCR_EL1, Sampling Filter Control Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:53]

SIMDm, bit [52]
When FEAT_SPE_EFT is implemented:

Otherwise:

FPm, bit [51]
When FEAT_SPE_EFT is implemented:

Otherwise:

STm, bit [50]
When FEAT_SPE_EFT is implemented:

Otherwise:

LDm, bit [49]
When FEAT_SPE_EFT is implemented:

Otherwise:

Bm, bit [48]
When FEAT_SPE_EFT is implemented:

Otherwise:

Bits [47:21]

SIMD, bit [20]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.SIMDm == 1:

When FEAT_SPE_EFT is implemented:

Otherwise:

FP, bit [19]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.FPm == 1:

When FEAT_SPE_EFT is implemented:

Otherwise:

ST, bit [18]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.STm == 1:

Otherwise:

LD, bit [17]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.LDm == 1:

Otherwise:

B, bit [16]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.Bm == 1:

Otherwise:

Bits [15:5]

FDS, bit [4]
When FEAT_SPE_FDS is implemented:

Otherwise:

FnE, bit [3]
When FEAT_SPEv1p2 is implemented:

Otherwise:

FL, bit [2]

FT, bit [1]

FE, bit [0]

Accessing PMSFCR_EL1

MRS <Xt>, PMSFCR_EL1

MSR PMSFCR_EL1, <Xt>

PMSFCR_EL1, Sampling Filter Control Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:53]

SIMDm, bit [52]When FEAT_SPE_EFT is implemented:

Otherwise:

FPm, bit [51]When FEAT_SPE_EFT is implemented:

Otherwise:

STm, bit [50]When FEAT_SPE_EFT is implemented:

Otherwise:

LDm, bit [49]When FEAT_SPE_EFT is implemented:

Otherwise:

Bm, bit [48]When FEAT_SPE_EFT is implemented:

Otherwise:

Bits [47:21]

SIMD, bit [20]When FEAT_SPE_EFT is implemented and PMSFCR_EL1.SIMDm == 1:

When FEAT_SPE_EFT is implemented:

Otherwise:

FP, bit [19]When FEAT_SPE_EFT is implemented and PMSFCR_EL1.FPm == 1:

When FEAT_SPE_EFT is implemented:

Otherwise:

ST, bit [18]When FEAT_SPE_EFT is implemented and PMSFCR_EL1.STm == 1:

Otherwise:

LD, bit [17]When FEAT_SPE_EFT is implemented and PMSFCR_EL1.LDm == 1:

Otherwise:

B, bit [16]When FEAT_SPE_EFT is implemented and PMSFCR_EL1.Bm == 1:

Otherwise:

Bits [15:5]

FDS, bit [4]When FEAT_SPE_FDS is implemented:

Otherwise:

FnE, bit [3]When FEAT_SPEv1p2 is implemented:

Otherwise:

FL, bit [2]

FT, bit [1]

FE, bit [0]

Accessing PMSFCR_EL1

MRS <Xt>, PMSFCR_EL1

MSR PMSFCR_EL1, <Xt>

SIMDm, bit [52]
When FEAT_SPE_EFT is implemented:

FPm, bit [51]
When FEAT_SPE_EFT is implemented:

STm, bit [50]
When FEAT_SPE_EFT is implemented:

LDm, bit [49]
When FEAT_SPE_EFT is implemented:

Bm, bit [48]
When FEAT_SPE_EFT is implemented:

SIMD, bit [20]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.SIMDm == 1:

FP, bit [19]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.FPm == 1:

ST, bit [18]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.STm == 1:

LD, bit [17]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.LDm == 1:

B, bit [16]
When FEAT_SPE_EFT is implemented and PMSFCR_EL1.Bm == 1:

FDS, bit [4]
When FEAT_SPE_FDS is implemented:

FnE, bit [3]
When FEAT_SPEv1p2 is implemented: