AMCNTENSET, Activity Monitors Count Enable Set Register

The AMCNTENSET characteristics are:

Purpose

Enable control bits for the architected and auxiliary activity monitors event counters, AMEVCNTR0<n> and AMEVCNTR1<n>.

Configuration

External register AMCNTENSET bits [31:0] are architecturally mapped to AArch64 System register AMCNTENSET0_EL0[31:0].

External register AMCNTENSET bits [63:32] are architecturally mapped to AArch64 System register AMCNTENSET1_EL0[31:0].

It is IMPLEMENTATION DEFINED whether AMCNTENSET is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented and FEAT_AMU_EXT64 is implemented. Otherwise, direct accesses to AMCNTENSET are RES0.

Attributes

AMCNTENSET is a 64-bit register.

This register is part of the AMU block.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0P115P114P113P112P111P110P19P18P17P16P15P14P13P12P11P10
RES0RAZ/WIP03P02P01P00

Bits [63:48]

Reserved, RES0.

P1<n>, bit [n+32], for n = 15 to 0

Activity monitor event counter enable bit for AMEVCNTR1<n>.

When N is less than 16, bits [15:N] are RAZ, where N is the value in AMCGCR.CG1NC.

Possible values of each bit are:

P1<n>Meaning
0b0

When read, means that AMEVCNTR1<n> is disabled.

0b1

When read, means that AMEVCNTR1<n> is enabled.

The reset behavior of this field is:

Bits [31:16]

Reserved, RES0.

Bits [15:4]

Reserved, RAZ/WI.

This field is reserved for additional architected activity monitor event counters, which Arm might define in a future version of the Activity Monitors architecture.

P0<n>, bit [n], for n = 3 to 0

Activity monitor event counter enable bit for AMEVCNTR0<n>.

Note

AMCGCR.CG0NC identifies the number of architected activity monitor event counters. In an implementation that includes FEAT_AMUv1, the number of architected activity monitor event counters is 4.

Possible values of each bit are:

P0<n>Meaning
0b0

When read, means that AMEVCNTR0<n> is disabled.

0b1

When read, means that AMEVCNTR0<n> is enabled.

The reset behavior of this field is:

Accessing AMCNTENSET

If there are no auxiliary monitor event counters implemented, reads of AMCNTENSET[63:32] are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.

Note

There are no implemented auxiliary activity monitor event counters when AMCFGR.NCG == 0b0000.

Accesses to this register use the following encodings:

Accessible at offset 0xC00 from AMU

Accesses on this interface are RO.


26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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