The AMEVTYPER0<n> characteristics are:
Provides information on the events that an architected activity monitor event counter AMEVCNTR0<n> counts.
External register AMEVTYPER0<n> bits [31:0] are architecturally mapped to AArch64 System register AMEVTYPER0<n>_EL0[31:0] when FEAT_AMU_EXT32 is implemented.
External register AMEVTYPER0<n> bits [63:0] are architecturally mapped to AArch64 System register AMEVTYPER0<n>_EL0[63:0] when FEAT_AMU_EXT64 is implemented.
External register AMEVTYPER0<n> bits [31:0] are architecturally mapped to AArch32 System register AMEVTYPER0<n>[31:0].
It is IMPLEMENTATION DEFINED whether AMEVTYPER0<n> is implemented in the Core power domain or in the Debug power domain.
This register is present only when FEAT_AMUv1 is implemented. Otherwise, direct accesses to AMEVTYPER0<n> are RES0.
AMEVTYPER0<n> is a:
This register is part of the AMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| RES0 | evtCount | ||||||||||||||||||||||||||||||
Reserved, RES0.
Event to count. The event number of the event that is counted by the architected activity monitor event counter AMEVCNTR0<n>. The value of this field is architecturally mandated for each architected counter.
The following table shows the mapping between required event numbers and the corresponding counters:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| evtCount | Meaning | Applies when |
|---|---|---|
| 0x0011 |
Processor frequency cycles | When n == 0 |
| 0x4004 |
Constant frequency cycles | When n == 1 |
| 0x0008 |
Instructions retired | When n == 2 |
| 0x4005 |
Memory stall cycles | When n == 3 |
Access to this field is RO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | evtCount | ||||||||||||||||||||||||||||||
Reserved, RES0.
Event to count. The event number of the event that is counted by the architected activity monitor event counter AMEVCNTR0<n>. The value of this field is architecturally mandated for each architected counter.
The following table shows the mapping between required event numbers and the corresponding counters:
The value of this field is an IMPLEMENTATION DEFINED choice of:
| evtCount | Meaning | Applies when |
|---|---|---|
| 0x0011 |
Processor frequency cycles | When n == 0 |
| 0x4004 |
Constant frequency cycles | When n == 1 |
| 0x0008 |
Instructions retired | When n == 2 |
| 0x4005 |
Memory stall cycles | When n == 3 |
Access to this field is RO.
If <n> is greater than or equal to the number of architected activity monitor event counters, reads of AMEVTYPER0<n> are RAZ. Software must treat reserved accesses as RES0. See 'Access requirements for reserved and unallocated registers'.
AMCGCR.CG0NC identifies the number of architected activity monitor event counters.
Accesses to this register use the following encodings:
Accessible at offset 0x400 + (8 * n) from AMU
Accesses on this interface are RO.
Accessible at offset 0x400 + (4 * n) from AMU
Accesses on this interface are RO.
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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