DBGWCR<n>

Holds control information for a watchpoint. Forms watchpoint n together with value register DBGWVR<n>_EL1.

Configuration

External register DBGWCR<n>_EL1 bits [31:0] are architecturally mapped to AArch64 System register DBGWCR<n>_EL1[31:0].

External register DBGWCR<n>_EL1 bits [63:32] are architecturally mapped to AArch64 System register DBGWCR<n>_EL1[63:32] when FEAT_Debugv8p9 is implemented.

External register DBGWCR<n>_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGWCR<n>[31:0].

Attributes

Field descriptions

Bits [63:32]

LBNX, bits [31:30]
When FEAT_Debugv8p9 is implemented:

Linked Breakpoint Number.

For Linked data address watchpoints, with DBGWCR<n>_EL1.LBN, specifies the index of the breakpoint linked to.

For all other watchpoint types, this field is ignored and reads of the register return an UNKNOWN value.

This field extends DBGWCR<n>_EL1.LBN to support up to 64 implemented breakpoints.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

SSCE, bit [29]
When FEAT_RME is implemented:

Security State Control Extended.

The fields that indicate when the watchpoint can be generated are: HMC, PAC, SSC, and SSCE. These fields must be considered in combination, and the values that are permitted for these fields are constrained.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

MASK, bits [28:24]

Address Mask. Only address ranges up to 2GB can be watched using a single mask.

MASK	Meaning
0b00000	No mask.
0b00011..0b11111	Number of address bits masked.

All other values are reserved.

Indicates the number of masked address bits, from 0b00011 masking 3 address bits (0x00000007 mask for address) to 0b11111 masking 31 address bits (0x7FFFFFFF mask for address).

If programmed with a reserved value, the watchpoint behaves as if one of the following:

DBGWCR<n>_EL1.MASK has been programmed with a defined value, which might be 0b00000 (no mask), other than for a direct read of DBGWCR<n>_EL1.
The watchpoint is disabled.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Bit [23]

WT2, bit [22]
When FEAT_BWE2 is implemented:

Watchpoint Type 2. With DBGWCR<n>_EL1.WT, specifies watchpoint type.

WT2	Meaning
0b0	Watchpoint n is an address match watchpoint.
0b1	Watchpoint n is an address mismatch watchpoint.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [21]

WT, bit [20]

Watchpoint type. Possible values are:

WT	Meaning
0b0	Unlinked data address match.
0b1	Linked data address match.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

LBN, bits [19:16]

Linked Breakpoint Number.

For Linked data address watchpoints, with DBGWCR<n>_EL1.LBNX when implemented, specifies the index of the breakpoint linked to.

For all other watchpoint types, this field is ignored and reads of the register return an UNKNOWN value.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

SSC, bits [15:14]

Security state control. Determines the Security states under which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the HMC and PAC fields.

For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions'.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

HMC, bit [13]

Higher mode control. Determines the debug perspective for deciding when a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and PAC fields.

For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions'.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

BAS, bits [12:5]

Byte address select. Each bit of this field selects whether a byte from within the word or double-word addressed by DBGWVR<n>_EL1 is being watched.

BAS	Description
xxxxxxx1	Match byte at DBGWVR<n>_EL1
xxxxxx1x	Match byte at DBGWVR<n>_EL1 + 1
xxxxx1xx	Match byte at DBGWVR<n>_EL1 + 2
xxxx1xxx	Match byte at DBGWVR<n>_EL1 + 3

In cases where DBGWVR<n>_EL1 addresses a double-word:

BAS	Description, if DBGWVR<n>_EL1[2] == 0
xxx1xxxx	Match byte at DBGWVR<n>_EL1 + 4
xx1xxxxx	Match byte at DBGWVR<n>_EL1 + 5
x1xxxxxx	Match byte at DBGWVR<n>_EL1 + 6
1xxxxxxx	Match byte at DBGWVR<n>_EL1 + 7

If DBGWVR<n>_EL1[2] == 1, only BAS[3:0] is used. Arm deprecates setting DBGWVR<n>_EL1[2] == 1.

The valid values for BAS are nonzero binary number all of whose set bits are contiguous. All other values are reserved and must not be used by software. See 'Reserved DBGWCR<n>.BAS values'.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

LSC, bits [4:3]

Load/store control. This field enables watchpoint matching on the type of access being made. Possible values of this field are:

LSC	Meaning
0b01	Match instructions that load from a watchpointed address.
0b10	Match instructions that store to a watchpointed address.
0b11	Match instructions that load from or store to a watchpointed address.

All other values are reserved, but must behave as if the watchpoint is disabled. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

PAC, bits [2:1]

Privilege of access control. Determines the Exception level or levels at which a Watchpoint debug event for watchpoint n is generated. This field must be interpreted along with the SSC and HMC fields.

For more information on the operation of the SSC, HMC, and PAC fields, see 'Execution conditions for which a watchpoint generates Watchpoint exceptions'.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

E, bit [0]

Enable watchpoint n.

E	Meaning
0b0	Watchpoint n disabled.
0b1	Watchpoint n enabled.

This field is ignored by the PE and treated as zero when all of the following are true:

Any of the following are true:
- HaltOnBreakpointOrWatchpoint() is FALSE and the Effective value of MDSCR_EL1.EMBWE is 0.
- HaltOnBreakpointOrWatchpoint() is TRUE and the Effective value of EDSCR2.EHBWE is 0.
FEAT_Debugv8p9 is implemented.
n >= 16.

The reset behavior of this field is:

On a Cold reset, this field resets to an architecturally UNKNOWN value.

Accessing DBGWCR<n>_EL1

When FEAT_Debugv8p9 is not implemented, this register is 32-bits wide and offset 0x80C + (16 * n) is reserved.

DBGWCR<n>_EL1 can be accessed through the external debug interface:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
LBNX		SSCE	MASK					RES0	WT2	RES0	WT	LBN				SSC		HMC	BAS								LSC		PAC		E

DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 - 63

Purpose

Configuration

Attributes

Field descriptions

Bits [63:32]

LBNX, bits [31:30]
When FEAT_Debugv8p9 is implemented:

Otherwise:

SSCE, bit [29]
When FEAT_RME is implemented:

Otherwise:

MASK, bits [28:24]

Bit [23]

WT2, bit [22]
When FEAT_BWE2 is implemented:

Otherwise:

Bit [21]

WT, bit [20]

LBN, bits [19:16]

SSC, bits [15:14]

HMC, bit [13]

BAS, bits [12:5]

LSC, bits [4:3]

PAC, bits [2:1]

E, bit [0]

Accessing DBGWCR<n>_EL1

DBGWCR<n>_EL1 can be accessed through the external debug interface:

DBGWCR<n>_EL1, Debug Watchpoint Control Registers, n = 0 - 63

Purpose

Configuration

Attributes

Field descriptions

Bits [63:32]

LBNX, bits [31:30]When FEAT_Debugv8p9 is implemented:

Otherwise:

SSCE, bit [29]When FEAT_RME is implemented:

Otherwise:

MASK, bits [28:24]

Bit [23]

WT2, bit [22]When FEAT_BWE2 is implemented:

Otherwise:

Bit [21]

WT, bit [20]

LBN, bits [19:16]

SSC, bits [15:14]

HMC, bit [13]

BAS, bits [12:5]

LSC, bits [4:3]

PAC, bits [2:1]

E, bit [0]

Accessing DBGWCR<n>_EL1

DBGWCR<n>_EL1 can be accessed through the external debug interface:

LBNX, bits [31:30]
When FEAT_Debugv8p9 is implemented:

SSCE, bit [29]
When FEAT_RME is implemented:

WT2, bit [22]
When FEAT_BWE2 is implemented: