GICD_ICPENDR<n>

These registers are available in all GIC configurations. If GICD_CTLR.DS==0, these registers are Common.

The number of implemented GICD_ICPENDR<n> registers is (GICD_TYPER.ITLinesNumber+1). Registers are numbered from 0.

GICD_ICPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8.

Accessing GICD_ICPENDR0 from a PE with GICR_TYPER.Processor_Number > 7 is CONSTRAINED UNPREDICTABLE:

Attributes

Field descriptions

Clear_pending_bit<x>, bit [x], for x = 31 to 0

For SPIs and PPIs, removes the pending state from interrupt number 32n + x. Reads and writes have the following behavior:

Clear_pending_bit<x>	Meaning
0b0	If read, indicates that the corresponding interrupt is not pending on any PE. If written, has no effect.
0b1	If read, indicates that the corresponding interrupt is pending, or active and pending. If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases: If the interrupt is an SGI. In this case, the write is ignored. The pending state of an SGI can be cleared using GICD_CPENDSGIR<n>. If the interrupt is not pending and is not active and pending. If the interrupt is a level-sensitive interrupt that is pending or active and pending for a reason other than a write to GICD_ISPENDR<n>. In this case, if the interrupt signal continues to be asserted, the interrupt remains pending or active and pending.

Clear_pending_bit<x>

Meaning

0b0

If read, indicates that the corresponding interrupt is not pending on any PE.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending.

If written, changes the state of the corresponding interrupt from pending to inactive, or from active and pending to active. This has no effect in the following cases:

If the interrupt is an SGI. In this case, the write is ignored. The pending state of an SGI can be cleared using GICD_CPENDSGIR<n>.
If the interrupt is not pending and is not active and pending.
If the interrupt is a level-sensitive interrupt that is pending or active and pending for a reason other than a write to GICD_ISPENDR<n>. In this case, if the interrupt signal continues to be asserted, the interrupt remains pending or active and pending.

The reset behavior of this field is:

On a GIC reset, this field resets to 0.

Additional information

For INTID m, when DIV and MOD are the integer division and modulo operations:

The corresponding GICD_ICPENDR<n> number, n, is given by n = m DIV 32.
The offset of the required GICD_ICPENDR is (0x200 + (4*n)).
The bit number of the required group modifier bit in this register is m MOD 32.

Accessing GICD_ICPENDR<n>

If GICD_CTLR.DS==0, unless the GICD_NSACR<n> registers permit Non-secure software to control Group 0 and Secure Group 1 interrupts, any bits that correspond to Group 0 or Secure Group 1 interrupts are accessible only by Secure accesses and are RAZ/WI to Non-secure accesses.

GICD_ICPENDR<n> can be accessed through the memory-mapped interfaces:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Clear_pending_bit31	Clear_pending_bit30	Clear_pending_bit29	Clear_pending_bit28	Clear_pending_bit27	Clear_pending_bit26	Clear_pending_bit25	Clear_pending_bit24	Clear_pending_bit23	Clear_pending_bit22	Clear_pending_bit21	Clear_pending_bit20	Clear_pending_bit19	Clear_pending_bit18	Clear_pending_bit17	Clear_pending_bit16	Clear_pending_bit15	Clear_pending_bit14	Clear_pending_bit13	Clear_pending_bit12	Clear_pending_bit11	Clear_pending_bit10	Clear_pending_bit9	Clear_pending_bit8	Clear_pending_bit7	Clear_pending_bit6	Clear_pending_bit5	Clear_pending_bit4	Clear_pending_bit3	Clear_pending_bit2	Clear_pending_bit1	Clear_pending_bit0

GICD_ICPENDR<n>, Interrupt Clear-Pending Registers, n = 0 - 31