TRCSYNCPR

External register TRCSYNCPR bits [31:0] are architecturally mapped to AArch64 System register TRCSYNCPR[31:0].

This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCSYNCPR are RES0.

Attributes

Field descriptions

Bits [31:5]

PERIOD, bits [4:0]

Defines the number of bytes of trace between each periodic trace protocol synchronization request.

PERIOD	Meaning
0b00000	Trace protocol synchronization is disabled.
0b01000	Trace protocol synchronization request occurs after 2⁸ bytes of trace.
0b01001	Trace protocol synchronization request occurs after 2⁹ bytes of trace.
0b01010	Trace protocol synchronization request occurs after 2¹⁰ bytes of trace.
0b01011	Trace protocol synchronization request occurs after 2¹¹ bytes of trace.
0b01100	Trace protocol synchronization request occurs after 2¹² bytes of trace.
0b01101	Trace protocol synchronization request occurs after 2¹³ bytes of trace.
0b01110	Trace protocol synchronization request occurs after 2¹⁴ bytes of trace.
0b01111	Trace protocol synchronization request occurs after 2¹⁵ bytes of trace.
0b10000	Trace protocol synchronization request occurs after 2¹⁶ bytes of trace.
0b10001	Trace protocol synchronization request occurs after 2¹⁷ bytes of trace.
0b10010	Trace protocol synchronization request occurs after 2¹⁸ bytes of trace.
0b10011	Trace protocol synchronization request occurs after 2¹⁹ bytes of trace.
0b10100	Trace protocol synchronization request occurs after 2²⁰ bytes of trace.

Other values are reserved. If a reserved value is programmed into PERIOD, then the behavior of the synchronization period counter is CONSTRAINED UNPREDICTABLE and one of the following behaviors occurs:

No trace protocol synchronization requests are generated by this counter.
Trace protocol synchronization requests occur at the specified period.
Trace protocol synchronization requests occur at some other UNKNOWN period which can vary.

The reset behavior of this field is:

On a Trace unit reset, this field resets to an architecturally UNKNOWN value.

Accessing TRCSYNCPR

Writes are CONSTRAINED UNPREDICTABLE if the trace unit is not in the Idle state.

TRCSYNCPR can be accessed through the external debug interface:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																											PERIOD

TRCSYNCPR, Trace Synchronization Period Register