The PMCFGR characteristics are:
Contains PMU-specific configuration data.
This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCFGR are RES0.
PMCFGR is in the Core power domain.
PMCFGR is a:
This register is part of the PMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | |||||||||||||||||||||||||||||||
| NCG | RES0 | SS | FZO | RES0 | UEN | WT | NA | EX | CCD | CC | SIZE | N | |||||||||||||||||||
Reserved, RES0.
Defines the number of counter groups implemented, minus one.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NCG | Meaning |
|---|---|
| 0b0000 |
One counter group implemented. |
| 0b0001 |
Two counter groups implemented. |
All other values are reserved.
FEAT_PMUv3_ICNTR implements the functionality identified by the value 0b0001.
Access to this field is RO.
Reserved, RES0.
Snapshot supported.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SS | Meaning |
|---|---|
| 0b0 |
Snapshot mechanism not supported. The locations 0x600-0x7FC and 0xE30-0xE3C are IMPLEMENTATION DEFINED. |
| 0b1 | Snapshot mechanism supported. If FEAT_PMUv3_SS is implemented, then the following registers are implemented:
Otherwise, locations 0x600-0x7FC and 0xE30-0xE3C contain IMPLEMENTATION DEFINED snapshot registers. |
FEAT_PMUv3_SS implements the functionality identified by the value 1.
If FEAT_PMUv3_SS is not implemented, a PMU might include an IMPLEMENTATION DEFINED snapshot mechanism, including one using the IMPLEMENTATION DEFINED registers 0x600-0x7FC and 0xE30-0xE3C.
Access to this field is RO.
Freeze-on-overflow supported.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| FZO | Meaning |
|---|---|
| 0b0 |
Freeze-on-overflow mechanism is not supported. PMCR_EL0.FZO is RES0. |
| 0b1 |
Freeze-on-overflow mechanism is supported. PMCR_EL0.FZO is RW. |
FEAT_PMUv3p7 implements the functionality added by the value 0b1.
From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 0b1.
Access to this field is RO.
Reserved, RES0.
User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
This feature is not supported, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
This feature is not supported, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
Export supported.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EX | Meaning |
|---|---|
| 0b0 |
PMCR_EL0.X is RES0. |
| 0b1 |
PMCR_EL0.X is read/write. |
Access to this field is RO.
Cycle counter has prescale.
This is RES1 if AArch32 is supported, and RAZ otherwise.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CCD | Meaning |
|---|---|
| 0b0 |
PMCR_EL0.D is RES0. |
| 0b1 |
PMCR_EL0.D is read/write. |
Access to this field is RO.
Dedicated cycle counter (counter 31) supported.
Reads as 0b1.
Access to this field is RO.
Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.
From Armv8.0, the largest counter is 64-bits, so the value of this field is 0b111111.
This field is used by software to determine the spacing of the counters in the memory-map. From Armv8.0, the counters are a doubleword-aligned addresses.
Reads as 0b111111.
Access to this field is RO.
Number of counters, minus one.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| N | Meaning |
|---|---|
| 0x00 |
Only PMCCNTR_EL0 implemented. |
| 0x01..0x20 |
Number of counters implemented, 2 to 33, minus one. |
All other values are reserved.
The count includes:
The cycle counter, PMCCNTR_EL0.
If FEAT_PMUv3_ICNTR is implemented, the Instruction Counter, PMICNTR_EL0.
For example, if PMCFGR.N == 0x07 then:
There are eight counters in total.
If FEAT_PMUv3_ICNTR is not implemented, this comprises 7 event counters and the cycle counter.
If FEAT_PMUv3_ICNTR is implemented, this comprises 6 event counters, the cycle counter, and the instruction counter.
Access to this field is RO.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NCG | RES0 | SS | FZO | RES0 | UEN | WT | NA | EX | CCD | CC | SIZE | N | |||||||||||||||||||
Defines the number of counter groups implemented, minus one.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| NCG | Meaning |
|---|---|
| 0b0000 |
One counter group implemented. |
| 0b0001 |
Two counter groups implemented. |
All other values are reserved.
FEAT_PMUv3_ICNTR implements the functionality identified by the value 0b0001.
Access to this field is RO.
Reserved, RES0.
Snapshot supported.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| SS | Meaning |
|---|---|
| 0b0 |
Snapshot mechanism not supported. The locations 0x600-0x7FC and 0xE30-0xE3C are IMPLEMENTATION DEFINED. |
| 0b1 | Snapshot mechanism supported. If FEAT_PMUv3_SS is implemented, then the following registers are implemented:
Otherwise, locations 0x600-0x7FC and 0xE30-0xE3C contain IMPLEMENTATION DEFINED snapshot registers. |
FEAT_PMUv3_SS implements the functionality identified by the value 1.
If FEAT_PMUv3_SS is not implemented, a PMU might include an IMPLEMENTATION DEFINED snapshot mechanism, including one using the IMPLEMENTATION DEFINED registers 0x600-0x7FC and 0xE30-0xE3C.
Access to this field is RO.
Freeze-on-overflow supported.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| FZO | Meaning |
|---|---|
| 0b0 |
Freeze-on-overflow mechanism is not supported. PMCR_EL0.FZO is RES0. |
| 0b1 |
Freeze-on-overflow mechanism is supported. PMCR_EL0.FZO is RW. |
FEAT_PMUv3p7 implements the functionality added by the value 0b1.
From Armv8.7, if FEAT_PMUv3 is implemented, the only permitted value is 0b1.
Access to this field is RO.
Reserved, RES0.
User-mode Enable Register supported. PMUSERENR_EL0 is not visible in the external debug interface, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
This feature is not supported, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
This feature is not supported, so this bit is RAZ.
Reads as 0b0.
Access to this field is RO.
Export supported.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| EX | Meaning |
|---|---|
| 0b0 |
PMCR_EL0.X is RES0. |
| 0b1 |
PMCR_EL0.X is read/write. |
Access to this field is RO.
Cycle counter has prescale.
This is RES1 if AArch32 is supported, and RAZ otherwise.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| CCD | Meaning |
|---|---|
| 0b0 |
PMCR_EL0.D is RES0. |
| 0b1 |
PMCR_EL0.D is read/write. |
Access to this field is RO.
Dedicated cycle counter (counter 31) supported.
Reads as 0b1.
Access to this field is RO.
Size of counters, minus one. This field defines the size of the largest counter implemented by the Performance Monitors Unit.
From Armv8.0, the largest counter is 64-bits, so the value of this field is 0b111111.
This field is used by software to determine the spacing of the counters in the memory-map. From Armv8.0, the counters are a doubleword-aligned addresses.
Reads as 0b111111.
Access to this field is RO.
Number of counters, minus one.
The value of this field is an IMPLEMENTATION DEFINED choice of:
| N | Meaning |
|---|---|
| 0x00 |
Only PMCCNTR_EL0 implemented. |
| 0x01..0x20 |
Number of counters implemented, 2 to 33, minus one. |
All other values are reserved.
The count includes:
The cycle counter, PMCCNTR_EL0.
If FEAT_PMUv3_ICNTR is implemented, the Instruction Counter, PMICNTR_EL0.
For example, if PMCFGR.N == 0x07 then:
There are eight counters in total.
If FEAT_PMUv3_ICNTR is not implemented, this comprises 7 event counters and the cycle counter.
If FEAT_PMUv3_ICNTR is implemented, this comprises 6 event counters, the cycle counter, and the instruction counter.
Access to this field is RO.
AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings:
[63:0] Accessible at offset 0xE00 from PMU
[31:0] Accessible at offset 0xE00 from PMU
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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