HFGWTR2

This register is present only when FEAT_FGT2 is implemented. Otherwise, direct accesses to HFGWTR2_EL2 are UNDEFINED.

Attributes

Field descriptions

Bits [63:3]

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

Trap MSR or MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 to EL2.

nRCWSMASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then unless the write generates a higher priority exception: MSR writes of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14.
0b1	MSR and MSRR writes of RCWSMASK_EL1 are not trapped by this mechanism.

nRCWSMASK_EL1

Meaning

0b0

If EL2 is implemented and enabled in the current Security state, then unless the write generates a higher priority exception:

MSR writes of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14.

0b1

MSR and MSRR writes of RCWSMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [1]

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented:

Trap MSR writes of PFAR_EL1 at EL1 using AArch64 to EL2.

nPFAR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MSR writes of PFAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.
0b1	MSR writes of PFAR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Accessing HFGWTR2_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HFGWTR2_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X[t, 64] = NVMem[0x2C8]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else X[t, 64] = HFGWTR2_EL2; elsif PSTATE.EL == EL3 then X[t, 64] = HFGWTR2_EL2;

MSR HFGWTR2_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b011

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem[0x2C8] = X[t, 64]; elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3.FGTEn2 == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.FGTEn2 == '0' then if EL3SDDUndef() then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x18); else HFGWTR2_EL2 = X[t, 64]; elsif PSTATE.EL == EL3 then HFGWTR2_EL2 = X[t, 64];

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																													nRCWSMASK_EL1	RES0	nPFAR_EL1

HFGWTR2_EL2, Hypervisor Fine-Grained Write Trap Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [63:3]

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

Otherwise:

Bit [1]

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented:

Otherwise:

Accessing HFGWTR2_EL2

MRS <Xt>, HFGWTR2_EL2

MSR HFGWTR2_EL2, <Xt>

HFGWTR2_EL2, Hypervisor Fine-Grained Write Trap Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [63:3]

nRCWSMASK_EL1, bit [2]When FEAT_THE is implemented:

Otherwise:

Bit [1]

nPFAR_EL1, bit [0]When FEAT_PFAR is implemented:

Otherwise:

Accessing HFGWTR2_EL2

MRS <Xt>, HFGWTR2_EL2

MSR HFGWTR2_EL2, <Xt>

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented: