AArch32 Registers
AArch64 Registers
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Proprietary Notice

ID_DFR0_EL1, AArch32 Debug Feature Register 0

The ID_DFR0_EL1 characteristics are:

Purpose

Provides top level information about the debug system in AArch32 state.

Must be interpreted with the Main ID Register, MIDR_EL1.

For general information about the interpretation of the ID registers see 'Principles of the ID scheme for fields in ID registers'.

Configuration

AArch64 System register ID_DFR0_EL1 bits [31:0] are architecturally mapped to AArch32 System register ID_DFR0[31:0].

Attributes

ID_DFR0_EL1 is a 64-bit register.

Field descriptions

When AArch32 is supported:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
TraceFiltPerfMonMProfDbgMMapTrcCopTrcMMapDbgCopSDbgCopDbg

Bits [63:32]

Reserved, RES0.

TraceFilt, bits [31:28]

Armv8.4 Self-hosted Trace Extension version.

The value of this field is an IMPLEMENTATION DEFINED choice of:

TraceFiltMeaning
0b0000

Armv8.4 Self-hosted Trace Extension not implemented.

0b0001

Armv8.4 Self-hosted Trace Extension implemented.

All other values are reserved.

FEAT_TRF implements the functionality added by the value 0b0001.

From Armv8.3, the permitted values are 0b0000 and 0b0001.

Access to this field is RO.

PerfMon, bits [27:24]

Performance Monitors Extension version.

This field does not follow the standard ID scheme, but uses the alternative ID scheme described in 'Alternative ID scheme used for the Performance Monitors Extension version'

The value of this field is an IMPLEMENTATION DEFINED choice of:

PerfMonMeaning
0b0000

Performance Monitors Extension not implemented.

0b0001

Performance Monitors Extension, PMUv1 implemented.

0b0010

Performance Monitors Extension, PMUv2 implemented.

0b0011

Performance Monitors Extension, PMUv3 implemented.

0b0100

PMUv3 for Armv8.1. As 0b0011, and adds support for:

  • Extended 16-bit PMEVTYPER<n>.evtCount field.
  • If EL2 is implemented, the HDCR.HPMD control.
0b0101

PMUv3 for Armv8.4. As 0b0100, and adds support for the PMMIR register.

0b0110

PMUv3 for Armv8.5. As 0b0101, and adds support for:

  • 64-bit event counters.
  • If EL2 is implemented, the HDCR.HCCD control.
  • If EL3 is implemented, the MDCR_EL3.SCCD control.
0b0111

PMUv3 for Armv8.7. As 0b0110, and adds support for:

  • The PMCR.FZO and, if EL2 is implemented, HDCR.HPMFZO controls.
  • If EL3 is implemented, the MDCR_EL3.{MPMX,MCCD} controls.
0b1000

PMUv3 for Armv8.8. As 0b0111, and:

  • Extends the Common event number space to include 0x0040 to 0x00BF and 0x4040 to 0x40BF.
  • Removes the CONSTRAINED UNPREDICTABLE behaviors if a reserved or unimplemented PMU event number is selected.
0b1001

PMUv3 for Armv8.9. As 0b1000, and:

  • Updates the definitions of existing PMU events.
  • Adds support for the EDECR.PME control.
0b1111

IMPLEMENTATION DEFINED form of performance monitors supported, PMUv3 not supported. Arm does not recommend this value for new implementations.

All other values are reserved.

FEAT_PMUv3 implements the functionality identified by the value 0b0011.

FEAT_PMUv3p1 implements the functionality identified by the value 0b0100.

FEAT_PMUv3p4 implements the functionality identified by the value 0b0101.

FEAT_PMUv3p5 implements the functionality identified by the value 0b0110.

FEAT_PMUv3p7 implements the functionality identified by the value 0b0111.

FEAT_PMUv3p8 implements the functionality identified by the value 0b1000.

FEAT_PMUv3p9 implements the functionality identified by the value 0b1001.

In any Armv8 implementation, the values 0b0001 and 0b0010 are not permitted.

From Armv8.1, if FEAT_PMUv3 is implemented, the value 0b0011 is not permitted.

From Armv8.4, if FEAT_PMUv3 is implemented, the value 0b0100 is not permitted.

From Armv8.5, if FEAT_PMUv3 is implemented, the value 0b0101 is not permitted.

From Armv8.7, if FEAT_PMUv3 is implemented, the value 0b0110 is not permitted.

From Armv8.8, if FEAT_PMUv3 is implemented, the value 0b0111 is not permitted.

From Armv8.9, if FEAT_PMUv3 is implemented, the value 0b1000 is not permitted.

Access to this field is RO.

MProfDbg, bits [23:20]

M-profile Debug. Support for memory-mapped debug model for M-profile processors.

The value of this field is an IMPLEMENTATION DEFINED choice of:

MProfDbgMeaning
0b0000

Not supported.

0b0001

Support for M-profile Debug architecture, with memory-mapped access.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.

Access to this field is RO.

MMapTrc, bits [19:16]

Memory-mapped Trace. Support for memory-mapped trace model.

The value of this field is an IMPLEMENTATION DEFINED choice of:

MMapTrcMeaning
0b0000

Not supported.

0b0001

Support for Arm trace architecture, with memory-mapped access.

All other values are reserved.

In Armv8-A, the permitted values are 0b0000 and 0b0001.

For more information, see the Arm® Embedded Trace Macrocell Architecture Specification, ETMv4 (ARM IHI 0064).

Access to this field is RO.

CopTrc, bits [15:12]

Support for System registers-based trace model, using registers in the coproc == 0b1110 encoding space.

The value of this field is an IMPLEMENTATION DEFINED choice of:

CopTrcMeaning
0b0000

Not supported.

0b0001

Support for Arm trace architecture, with System registers access.

All other values are reserved.

In Armv8-A, the permitted values are 0b0000 and 0b0001.

For more information, see the Arm® Embedded Trace Macrocell Architecture Specification, ETMv4 (ARM IHI 0064).

Access to this field is RO.

MMapDbg, bits [11:8]

Memory-mapped Debug. Support for Armv7 memory-mapped debug model for A and R-profile processors.

The value of this field is an IMPLEMENTATION DEFINED choice of:

MMapDbgMeaning
0b0000

Not supported.

0b0100

Support for Armv7, v7 Debug architecture, with memory-mapped access.

0b0101

Support for Armv7, v7.1 Debug architecture, with memory-mapped access.

All other values are reserved.

In Armv8-A, the only permitted value is 0b0000.

The optional memory map defined by Armv8 is not compatible with Armv7.

Access to this field is RO.

CopSDbg, bits [7:4]

Support for a System registers-based Secure debug model, using registers in the coproc = 0b1110 encoding space, for an A-profile processor that includes EL3.

If EL3 is not implemented and the implemented Security state is Non-secure state, this field is RES0. Otherwise, this field reads the same as bits [3:0].

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

CopDbg, bits [3:0]

Debug architecture version. Indicates presence of Armv8 debug architecture.

The value of this field is an IMPLEMENTATION DEFINED choice of:

CopDbgMeaning
0b0000

Not supported.

0b0010

Armv6, v6 Debug architecture, with System registers access.

0b0011

Armv6, v6.1 Debug architecture, with System registers access.

0b0100

Armv7, v7 Debug architecture, with System registers access.

0b0101

Armv7, v7.1 Debug architecture, with System registers access.

0b0110

Armv8 debug architecture.

0b0111

Armv8 debug architecture with Virtualization Host Extensions.

0b1000

Armv8.2 debug architecture, FEAT_Debugv8p2.

0b1001

Armv8.4 debug architecture, FEAT_Debugv8p4.

0b1010

Armv8.8 debug architecture, FEAT_Debugv8p8.

0b1011

Armv8.9 debug architecture, FEAT_Debugv8p9.

All other values are reserved.

The values 0b0000, 0b0010, 0b0011, 0b0100, and 0b0101 are not permitted in Armv8.

FEAT_VHE implements the functionality identified by the value 0b0111.

FEAT_Debugv8p2 implements the functionality identified by the value 0b1000.

FEAT_Debugv8p4 implements the functionality identified by the value 0b1001.

FEAT_Debugv8p8 implements the functionality identified by the value 0b1010.

FEAT_Debugv8p9 implements the functionality identified by the value 0b1011.

From Armv8.1, when FEAT_VHE is implemented the value 0b0110 is not permitted.

From Armv8.2, the values 0b0110 and 0b0111 are not permitted.

From Armv8.4, the value 0b1000 is not permitted.

From Armv8.8, the value 0b1001 is not permitted.

From Armv8.9, the value 0b1010 is not permitted.

Access to this field is RO.

Otherwise:

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
UNKNOWN
UNKNOWN

Bits [63:0]

Reserved, UNKNOWN.

Accessing ID_DFR0_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ID_DFR0_EL1

op0op1CRnCRmop2
0b110b0000b00000b00010b010

if PSTATE.EL == EL0 then if IsFeatureImplemented(FEAT_IDST) then if EL2Enabled() && HCR_EL2.TGE == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else AArch64.SystemAccessTrap(EL1, 0x18); else UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TID3 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else X[t, 64] = ID_DFR0_EL1; elsif PSTATE.EL == EL2 then X[t, 64] = ID_DFR0_EL1; elsif PSTATE.EL == EL3 then X[t, 64] = ID_DFR0_EL1;

AArch32 Registers
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Proprietary Notice

26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6

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