The GICC_CTLR characteristics are:
Controls the CPU interface, including enabling of interrupt groups, interrupt signal bypass, binary point registers used, and separation of priority drop and interrupt deactivation.
If the GIC implementation supports two Security states, independent EOI controls are provided for accesses from each Security state. Secure accesses handle both Group 0 and Group 1 interrupts, and Non-secure accesses handle Group 1 interrupts only.
This register is present only when FEAT_GICv3_LEGACY is implemented. Otherwise, direct accesses to GICC_CTLR are RES0.
In a GIC implementation that supports two Security states:
GICC_CTLR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | EOImodeNS | RES0 | IRQBypDisGrp1 | FIQBypDisGrp1 | RES0 | EnableGrp1 | |||||||||||||||||||||||||
Reserved, RES0.
Controls the behavior of Non-secure accesses to GICC_EOIR, GICC_AEOIR, and GICC_DIR.
| EOImodeNS | Meaning |
|---|---|
| 0b0 |
GICC_EOIR and GICC_AEOIR provide both priority drop and interrupt deactivation functionality. Accesses to GICC_DIR are UNPREDICTABLE. |
| 0b1 |
GICC_EOIR and GICC_AEOIR provide priority drop functionality only. GICC_DIR provides interrupt deactivation functionality. |
An implementation is permitted to make this bit RAO/WI.
The reset behavior of this field is:
Reserved, RES0.
When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 1:
| IRQBypDisGrp1 | Meaning |
|---|---|
| 0b0 |
The bypass IRQ signal is signaled to the PE. |
| 0b1 |
The bypass IRQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 1:
| FIQBypDisGrp1 | Meaning |
|---|---|
| 0b0 |
The bypass FIQ signal is signaled to the PE. |
| 0b1 |
The bypass FIQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DFB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
Reserved, RES0.
This Non-secure field enables the signaling of Group 1 interrupts by the CPU interface to a target PE:
| EnableGrp1 | Meaning |
|---|---|
| 0b0 |
Group 1 interrupt signaling is disabled. |
| 0b1 |
Group 1 interrupt signaling is enabled. |
The reset behavior of this field is:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | EOImodeNS | EOImodeS | IRQBypDisGrp1 | FIQBypDisGrp1 | IRQBypDisGrp0 | FIQBypDisGrp0 | CBPR | FIQEn | RES0 | EnableGrp1 | EnableGrp0 | ||||||||||||||||||||
Reserved, RES0.
Controls the behavior of Non-secure accesses to GICC_EOIR, GICC_AEOIR, and GICC_DIR.
| EOImodeNS | Meaning |
|---|---|
| 0b0 |
GICC_EOIR and GICC_AEOIR provide both priority drop and interrupt deactivation functionality. Accesses to GICC_DIR are UNPREDICTABLE. |
| 0b1 |
GICC_EOIR and GICC_AEOIR provide priority drop functionality only. GICC_DIR provides interrupt deactivation functionality. |
An implementation is permitted to make this bit RAO/WI.
The reset behavior of this field is:
Controls the behavior of Secure accesses to GICC_EOIR, GICC_AEOIR, and GICC_DIR.
| EOImodeS | Meaning |
|---|---|
| 0b0 |
GICC_EOIR and GICC_AEOIR provide both priority drop and interrupt deactivation functionality. Accesses to GICC_DIR are UNPREDICTABLE. |
| 0b1 |
GICC_EOIR and GICC_AEOIR provide priority drop functionality only. GICC_DIR provides interrupt deactivation functionality. |
An implementation is permitted to make this bit RAO/WI.
This field shares state with GICC_CTLR.EOImode.
The reset behavior of this field is:
When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 1:
| IRQBypDisGrp1 | Meaning |
|---|---|
| 0b0 |
The bypass IRQ signal is signaled to the PE. |
| 0b1 |
The bypass IRQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 1:
| FIQBypDisGrp1 | Meaning |
|---|---|
| 0b0 |
The bypass FIQ signal is signaled to the PE. |
| 0b1 |
The bypass FIQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DFB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 0:
| IRQBypDisGrp0 | Meaning |
|---|---|
| 0b0 |
The bypass IRQ signal is signaled to the PE. |
| 0b1 |
The bypass IRQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 0:
| FIQBypDisGrp0 | Meaning |
|---|---|
| 0b0 |
The bypass FIQ signal is signaled to the PE. |
| 0b1 |
The bypass FIQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts:
| CBPR | Meaning |
|---|---|
| 0b0 | GICC_BPR determines preemption for Group 0 interrupts only. GICC_ABPR determines preemption for Group 1 interrupts. |
| 0b1 |
GICC_BPR determines preemption for both Group 0 and Group 1 interrupts. |
This field is an alias of ICC_CTLR_EL3.CBPR_EL1NS.
In a GIC that supports two Security states, when CBPR == 1:
The reset behavior of this field is:
Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal:
| FIQEn | Meaning |
|---|---|
| 0b0 |
Group 0 interrupts are signaled using the IRQ signal. |
| 0b1 |
Group 0 interrupts are signaled using the FIQ signal. |
Group 1 interrupts are signaled using the IRQ signal only.
If an implementation supports two Security states, this bit is permitted to be RAO/WI.
The reset behavior of this field is:
Reserved, RES0.
This Non-secure field enables the signaling of Group 1 interrupts by the CPU interface to a target PE:
| EnableGrp1 | Meaning |
|---|---|
| 0b0 |
Group 1 interrupt signaling is disabled. |
| 0b1 |
Group 1 interrupt signaling is enabled. |
The reset behavior of this field is:
Enables the signaling of Group 0 interrupts by the CPU interface to a target PE:
| EnableGrp0 | Meaning |
|---|---|
| 0b0 |
Group 0 interrupt signaling is disabled. |
| 0b1 |
Group 0 interrupt signaling is enabled. |
The reset behavior of this field is:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | EOImode | IRQBypDisGrp1 | FIQBypDisGrp1 | IRQBypDisGrp0 | FIQBypDisGrp0 | CBPR | FIQEn | RES0 | EnableGrp1 | EnableGrp0 | |||||||||||||||||||||
Reserved, RES0.
Controls the behavior of accesses to GICC_EOIR, GICC_AEOIR, and GICC_DIR.
| EOImode | Meaning |
|---|---|
| 0b0 |
GICC_EOIR and GICC_AEOIR provide both priority drop and interrupt deactivation functionality. Accesses to GICC_DIR are UNPREDICTABLE. |
| 0b1 |
GICC_EOIR and GICC_AEOIR provide priority drop functionality only. GICC_DIR provides interrupt deactivation functionality. |
An implementation is permitted to make this bit RAO/WI.
This field shares state with GICC_CTLR.EOImodeS.
The reset behavior of this field is:
When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 1:
| IRQBypDisGrp1 | Meaning |
|---|---|
| 0b0 |
The bypass IRQ signal is signaled to the PE. |
| 0b1 |
The bypass IRQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 1:
| FIQBypDisGrp1 | Meaning |
|---|---|
| 0b0 |
The bypass FIQ signal is signaled to the PE. |
| 0b1 |
The bypass FIQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DFB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
When the signaling of IRQs by the CPU interface is disabled, this field partly controls whether the bypass IRQ signal is signaled to the PE for Group 0:
| IRQBypDisGrp0 | Meaning |
|---|---|
| 0b0 |
The bypass IRQ signal is signaled to the PE. |
| 0b1 |
The bypass IRQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
When the signaling of FIQs by the CPU interface is disabled, this field partly controls whether the bypass FIQ signal is signaled to the PE for Group 0:
| FIQBypDisGrp0 | Meaning |
|---|---|
| 0b0 |
The bypass FIQ signal is signaled to the PE. |
| 0b1 |
The bypass FIQ signal is not signaled to the PE. |
If System register access is enabled for EL3 and ICC_SRE_EL3.DIB == 1, this field is RAO/WI.
If System register access is enabled for EL1, this field is ignored.
If an implementation does not support legacy interrupts, this bit is permitted to be RAO/WI.
For more information, see 'Interrupt bypass support' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
The reset behavior of this field is:
Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts:
| CBPR | Meaning |
|---|---|
| 0b0 | GICC_BPR determines preemption for Group 0 interrupts only. GICC_ABPR determines preemption for Group 1 interrupts. |
| 0b1 |
GICC_BPR determines preemption for both Group 0 and Group 1 interrupts. |
This field is an alias of ICC_CTLR_EL3.CBPR_EL1NS.
In a GIC that supports two Security states, when CBPR == 1:
The reset behavior of this field is:
Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal:
| FIQEn | Meaning |
|---|---|
| 0b0 |
Group 0 interrupts are signaled using the IRQ signal. |
| 0b1 |
Group 0 interrupts are signaled using the FIQ signal. |
Group 1 interrupts are signaled using the IRQ signal only.
If an implementation supports two Security states, this bit is permitted to be RAO/WI.
The reset behavior of this field is:
Reserved, RES0.
This Non-secure field enables the signaling of Group 1 interrupts by the CPU interface to a target PE:
| EnableGrp1 | Meaning |
|---|---|
| 0b0 |
Group 1 interrupt signaling is disabled. |
| 0b1 |
Group 1 interrupt signaling is enabled. |
The reset behavior of this field is:
Enables the signaling of Group 0 interrupts by the CPU interface to a target PE:
| EnableGrp0 | Meaning |
|---|---|
| 0b0 |
Group 0 interrupt signaling is disabled. |
| 0b1 |
Group 0 interrupt signaling is enabled. |
The reset behavior of this field is:
This register is used only when System register access is not enabled. When System register access is enabled:
| Component | Offset | Instance |
|---|---|---|
| GIC CPU interface | 0x0000 | GICC_CTLR |
This interface is accessible as follows:
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.