The TRCPIDR2 characteristics are:
Provides discovery information about the component.
For additional information, see the CoreSight Architecture Specification.
This register is present only when FEAT_ETE is implemented and FEAT_TRC_EXT is implemented. Otherwise, direct accesses to TRCPIDR2 are RES0.
TRCPIDR2 is a 32-bit register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RES0 | REVISION | JEDEC | DES_1 |
Reserved, RES0.
Component major revision.
TRCPIDR2.REVISION and TRCPIDR3.REVAND together form the revision number of the component, with TRCPIDR2.REVISION being the most significant part and TRCPIDR3.REVAND the least significant part.
When a component is changed, TRCPIDR2.REVISION or TRCPIDR3.REVAND are increased to ensure that software can differentiate the different revisions of the component. TRCPIDR3.REVAND should be set to 0b0000 when TRCPIDR2.REVISION is increased.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
JEDEC-assigned JEP106 implementer code is used.
Reads as 0b1.
Access to this field is RO.
Designer, JEP106 identification code, bits [6:4].
JEP106 identification and continuation codes, which are stored as follows:
These codes indicate the designer of the component and not the implementer, except where the two are the same. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.
A JEDEC code takes the following form:
The parity bit in the JEP106 identification code is not included.
For example, Arm Limited is assigned the code 0x7F 0x7F 0x7F 0x7F 0x3B.
This field has an IMPLEMENTATION DEFINED value.
Access to this field is RO.
External debugger accesses to this register are unaffected by the OS Lock.
Component | Offset | Instance |
---|---|---|
ETE | 0xFE8 | TRCPIDR2 |
This interface is accessible as follows:
26/03/2024 09:49; 67c0ae5282a7629ba0ea0ba7267b43cd4f7939f6
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